library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is 
  port (
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
  );
end; 

architecture struct of top is

  component bin2seg is 
    port (
      number_i:       in  unsigned(3 downto 0);
      seg_o:          out std_ulogic_vector(6 downto 0)
    );
  end component;

  component adder is 
    port (
      a_i:            in  unsigned(3 downto 0);
      b_i:            in  unsigned(3 downto 0);
      sum_o:          out unsigned(3 downto 0)
    );
  end component;
  
  signal a, b, sum : unsigned(3 downto 0);
  
begin
  
  a <= unsigned(SW(3 downto 0));
  b <= unsigned(SW(8 downto 5));
       
  bin2seg_i0 : bin2seg
    port map (
      number_i => a,
      seg_o    => HEX0);
      
  bin2seg_i1 : bin2seg
    port map (
      number_i => b,
      seg_o    => HEX1);
          
 -- Hier bin2seg für die Summe und adder einfügen    
      
  LEDR <= SW;
			   
end; -- architecture