library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_tb is
end; 

architecture beh of top_tb is

  component top
  port (
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
    );
  end component;

  signal number1, number2    : unsigned(4 downto 0);
  signal switch              : std_ulogic_vector(9 downto 0);
  signal hex0, hex1, hex2    : std_ulogic_vector(6 downto 0);
  signal ledr                : std_ulogic_vector(9 downto 0);

begin
  
  top_i0 : top
    port map (
      SW                  => switch,
      LEDR                => ledr,
      HEX0                => hex0,
      HEX1                => hex1,
      HEX2                => hex2);
       
  switch(4 downto 0) <= std_ulogic_vector(number1);
  switch(9 downto 5) <= std_ulogic_vector(number2); 
  
  process
  begin
    number1 <= "00000";
    number2 <= "00000";
    wait for 10 us; 
    for i in 0 to 31 loop
      number1 <= number1 + 1;
      for v in 0 to 31 loop
        number2 <= number2 + 1;
        wait for 10 us;
      end loop;
    end loop;  
  end process; 

end; -- architecture