library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Frequency dividing counter
-- Enable signal is generated every second
-- with a 50 MHz clock. 

entity counter_long is 
  port (
    clk_i:      in std_ulogic;
    reset_ni:   in std_ulogic; 
    enable_o:   out std_ulogic
  );
end; 

architecture rtl of counter_long is  
  signal count_reg, new_count : unsigned(0 downto 0);
begin

  comb_p : process(count_reg)
  begin
    -- Here we go
  end process comb_p;  

  -- The sequential process for flipflop instantiation
  -- All signal assignments in this process will result in flipflops.
  count_p : process (clk_i, reset_ni)
  begin
    if reset_ni = '0' then
      count_reg <= (others => '0');
    elsif rising_edge(clk_i) then
      count_reg <= new_count;
    end if; 
  end process count_p;  
 			   
end; -- architecture