library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- First sequential circuit counts modulo 256
-- The circuit has two inputs, clk_i and reset_ni
-- and one output count_o. 
-- The function of the circuit is a counter which will increment by one
-- with each rising clock edge of clk_i
-- The counter uses flipflops with asynchronous reset for initializing
-- the flipflips and hence the counterstate to 0. Setting reset_ni to "0" will
-- reset the flipflops. 
-- The signal count_reg represents the Q outputs of the flipflops, while 
-- the signal new_count is connected the D inputs of the flipflops. 
-- The flipflops result from the description in the count_p process. 
-- The combinational logic which computes the new state of the flipflops
-- based on the current state is in new_count_p
-- The count_p process template is the way to infer flipflops. 

entity counter is 
  port (
    clk_i:      in std_ulogic;
    reset_ni:   in std_ulogic; 
    enable_i:   in std_ulogic;
    count_o:    out unsigned(7 downto 0)
  );
end; 

architecture rtl of counter is  
  signal count_reg, new_count : unsigned(7 downto 0);
begin

  -- Combinational process which computes the new state
  -- of the registers from the current state. This process will not
  -- infer registers but combinational logic (here an adder).  
  new_count_p : process(count_reg, enable_i)
  begin
    new_count <= count_reg; 
    if enable_i = '1' then
      new_count <= count_reg + 1;
    end if;
  end process new_count_p;  

  -- The sequential process for flipflop instantiation
  -- All signal assignments in this process will result in flipflops.
  count_p : process (clk_i, reset_ni)
  begin
    if reset_ni = '0' then
      -- This is the asynchronous reset of the flipflops
      -- with negative logic, i.e. when the reset_ni is "0", then
      -- the flipflops are asynchronously reset. 
      count_reg <= "00000000";
    elsif rising_edge(clk_i) then
      -- Here the new state is assigned to the registers. 
      count_reg <= new_count;
    end if; 
  end process count_p;  

  count_o <= count_reg;    
 			   
end; -- architecture