library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_tb is
end; 

architecture beh of top_tb is

  component top 
  port (
    CLOCK_50:   in  std_ulogic;
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches  
    KEY:        in  std_ulogic_vector(3 downto 0);
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
    );
  end component;

  signal clk, reset_n : std_ulogic;
  signal inc          : std_ulogic;

  signal switch : std_ulogic_vector(9 downto 0);
  signal key    : std_ulogic_vector(3 downto 0);
  signal ledr   : std_ulogic_vector(9 downto 0);
  signal hex0, hex1, hex2 : std_ulogic_vector(6 downto 0); 

begin
  
  top_i0 : top
    port map (
      CLOCK_50            => clk,
      SW                  => switch,
      KEY                 => key,
      LEDR                => ledr,
      HEX0                => hex0,
      HEX1                => hex1,
      HEX2                => hex2);
           
  key(0) <= inc;
  key(1) <= reset_n; 
  key(3 downto 2) <= "00"; 
  
           
  clk_p : process
  begin
    clk <= '0';
    wait for 1 us;
    clk <= '1';
    wait for 1 us; 
  end process clk_p;

  reset_p : process
  begin
    reset_n <= '0';
    wait for 15500 ns; 
    reset_n <= '1';  
    wait; 
  end process reset_p;
  
  incr_p : process
  begin
    inc <= '1'; 
    wait for 25100 ns;
    for i in 0 to 100 loop
      inc <= '0';
      wait for 20 us;
      inc <= '1';
      wait for 20 us;
    end loop; 
  end process incr_p;
    
   
  switch <= "0000000000";  

end; -- architecture