library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- Finite State Machine (FSM) for rising edge detection -- The edge_o signal will go to "1", when there is a 01 sequence -- at the key_i input. entity qdec is port ( clk_i: in std_ulogic; reset_ni: in std_ulogic; s1_i: in std_ulogic; s2_i: in std_ulogic; rising_edge_s1_i: in std_ulogic; falling_edge_s1_i: in std_ulogic; rising_edge_s2_i: in std_ulogic; falling_edge_s2_i: in std_ulogic; up_o: out std_ulogic; enable_o: out std_ulogic ); end; architecture rtl of qdec is type state_type is (XXXX_s); signal current_state, next_state : state_type; begin next_state_and_output_p : process(current_state, s1_i, s2_i, rising_edge_s1_i, falling_edge_s1_i, rising_edge_s2_i, falling_edge_s2_i) begin up_o <= '0'; enable_o <= '0'; next_state <= current_state; case current_state is when XXXX_s => -- Your code goes here... when others => next_state <= current_state; end case; end process next_state_and_output_p; -- The sequential process for flipflop instantiation -- All signal assignments in this process will result in flipflops. state_reg_p : process (clk_i, reset_ni) begin if reset_ni = '0' then current_state <= waiting_s; elsif rising_edge(clk_i) then current_state <= next_state; end if; end process state_reg_p; end; -- architecture