library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_tb is
end; 

architecture beh of top_tb is

  component top 
  port (
    CLOCK_50:   in  std_ulogic;
    GPIO_1:     in  std_ulogic_vector(35 downto 0); 
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches  
    KEY:        in  std_ulogic_vector(3 downto 0);
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
    );
  end component;

  signal clk, reset_n : std_ulogic;

  signal switch : std_ulogic_vector(9 downto 0);
  signal key    : std_ulogic_vector(3 downto 0);
  signal ledr   : std_ulogic_vector(9 downto 0);
  signal hex0, hex1, hex2 : std_ulogic_vector(6 downto 0); 
  signal gpio_1 : std_ulogic_vector(35 downto 0);
  signal s1, s2 : std_ulogic; 

begin
  
  top_i0 : top
    port map (
      CLOCK_50            => clk,
      GPIO_1              => gpio_1,
      SW                  => switch,
      KEY                 => key,
      LEDR                => ledr,
      HEX0                => hex0,
      HEX1                => hex1,
      HEX2                => hex2);
                     
  clk_p : process
  begin
    clk <= '0';
    wait for 1 us;
    clk <= '1';
    wait for 1 us; 
  end process clk_p;

  reset_p : process
  begin
    reset_n <= '0';
    wait for 15500 ns; 
    reset_n <= '1';  
    wait; 
  end process reset_p;
  
  s1_p : process
  begin
    for i in 0 to 3 loop
      s1 <= '0';
      wait for 50 us;
      s1 <= '1';
      wait for 50 us;
    end loop; 
    wait for 50 us; 
  end process s1_p;

  s2_p : process
  begin
    s2 <= '0';  
    wait for 25 us;
    for i in 0 to 1000 loop
      s2 <= '0';
      wait for 50 us;
      s2 <= '1';
      wait for 50 us;
    end loop; 
    wait; 
  end process s2_p;
    
  GPIO_1(0) <= s1;
  GPIO_1(1) <= s2; 
  GPIO_1(35 downto 2) <= (others => '0'); 
 
  switch <= "0000000000";  
  key(3 downto 1) <= "000"; 
  key(0) <= reset_n;  

end; -- architecture