==== Code für den Zustandsautomaten der Flankenerkennung ====
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Finite State Machine (FSM) for rising edge detection
-- The edge_o signal will go to "1", when there is a 01 sequence
-- at the key_i input.
entity edge is
port (
clk_i: in std_ulogic;
reset_ni: in std_ulogic;
key_i: in std_ulogic;
edge_o: out std_ulogic
);
end;
architecture rtl of edge is
type state_type is (start_s, null_s, eins_s);
signal current_state, next_state : state_type;
begin
next_state_and_output_p : process(current_state, key_i)
begin
edge_o <= '0';
next_state <= current_state;
case current_state is
when start_s =>
next_state <= null_s;
when null_s =>
if key_i = '1' then
next_state <= eins_s;
end if;
when eins_s =>
edge_o <= '1';
next_state <= null_s;
when others =>
next_state <= current_state;
end case;
end process next_state_and_output_p;
-- The sequential process for flipflop instantiation
-- All signal assignments in this process will result in flipflops.
state_reg_p : process (clk_i, reset_ni)
begin
if reset_ni = '0' then
current_state <= start_s;
elsif rising_edge(clk_i) then
current_state <= next_state;
end if;
end process state_reg_p;
end; -- architecture
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- First sequential circuit counts modulo 256
-- The circuit has two inputs, clk_i and reset_ni
-- and one output count_o.
-- The function of the circuit is a counter which will increment by one
-- with each rising clock edge of clk_i
-- The counter uses flipflops with asynchronous reset for initializing
-- the flipflips and hence the counterstate to 0. Setting reset_ni to "0" will
-- reset the flipflops.
-- The signal count_reg represents the Q outputs of the flipflops, while
-- the signal new_count is connected the D inputs of the flipflops.
-- The flipflops result from the description in the count_p process.
-- The combinational logic which computes the new state of the flipflops
-- based on the current state is in new_count_p
-- The count_p process template is the way to infer flipflops.
entity counter is
port (
clk_i: in std_ulogic;
reset_ni: in std_ulogic;
enable_i: in std_ulogic;
count_o: out unsigned(7 downto 0)
);
end;
architecture rtl of counter is
signal count_reg, new_count : unsigned(7 downto 0);
begin
-- Combinational process which computes the new state
-- of the registers from the current state. This process will not
-- infer registers but combinational logic (here an adder).
new_count_p : process(count_reg, enable_i)
begin
new_count <= count_reg;
if enable_i = '1' then
new_count <= count_reg + 1;
end if;
end process new_count_p;
-- The sequential process for flipflop instantiation
-- All signal assignments in this process will result in flipflops.
count_p : process (clk_i, reset_ni)
begin
if reset_ni = '0' then
-- This is the asynchronous reset of the flipflops
-- with negative logic, i.e. when the reset_ni is "0", then
-- the flipflops are asynchronously reset.
count_reg <= "00000000";
elsif rising_edge(clk_i) then
-- Here the new state is assigned to the registers.
count_reg <= new_count;
end if;
end process count_p;
count_o <= count_reg;
end; -- architecture
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top is
port (
CLOCK_50: in std_ulogic; -- 50 MHz Clock input
SW: in std_ulogic_vector(9 downto 0); -- Switches
KEY: in std_ulogic_vector(3 downto 0); -- Keys
LEDR: out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
HEX0: out std_ulogic_vector(6 downto 0); -- 7 Segment Display
HEX1: out std_ulogic_vector(6 downto 0); -- 7 Segment Display
HEX2: out std_ulogic_vector(6 downto 0) -- 7 Segment Display
);
end;
architecture struct of top is
component bin2seg is
port (
number_i: in unsigned(3 downto 0);
seg_o: out std_ulogic_vector(6 downto 0)
);
end component;
component counter is
port (
clk_i: in std_ulogic;
reset_ni: in std_ulogic;
enable_i: in std_ulogic;
count_o: out unsigned(7 downto 0)
);
end component;
component edge is
port (
clk_i: in std_ulogic;
reset_ni: in std_ulogic;
key_i: in std_ulogic;
edge_o: out std_ulogic
);
end component;
signal count : unsigned(7 downto 0);
signal enable : std_ulogic;
begin
bin2seg_i0 : bin2seg
port map (
number_i => count(3 downto 0),
seg_o => HEX0);
bin2seg_i1 : bin2seg
port map (
number_i => count(7 downto 4),
seg_o => HEX1);
counter_i0 : counter
port map (
clk_i => CLOCK_50,
reset_ni => KEY(1),
enable_i => enable,
count_o => count);
edge_i0 : edge
port map (
clk_i => CLOCK_50,
reset_ni => KEY(1),
key_i => KEY(0),
edge_o => enable);
LEDR(7 downto 0) <= std_ulogic_vector(count);
LEDR(9 downto 8) <= "00";
HEX2 <= "1111111";
end; -- architecture
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_tb is
end;
architecture beh of top_tb is
component top
port (
CLOCK_50: in std_ulogic;
SW: in std_ulogic_vector(9 downto 0); -- Switches
KEY: in std_ulogic_vector(3 downto 0);
LEDR: out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
HEX0: out std_ulogic_vector(6 downto 0); -- 7 Segment Display
HEX1: out std_ulogic_vector(6 downto 0); -- 7 Segment Display
HEX2: out std_ulogic_vector(6 downto 0) -- 7 Segment Display
);
end component;
signal clk, reset_n : std_ulogic;
signal inc : std_ulogic;
signal switch : std_ulogic_vector(9 downto 0);
signal key : std_ulogic_vector(3 downto 0);
signal ledr : std_ulogic_vector(9 downto 0);
signal hex0, hex1, hex2 : std_ulogic_vector(6 downto 0);
begin
top_i0 : top
port map (
CLOCK_50 => clk,
SW => switch,
KEY => key,
LEDR => ledr,
HEX0 => hex0,
HEX1 => hex1,
HEX2 => hex2);
key(0) <= inc;
key(1) <= reset_n;
key(3 downto 2) <= "00";
clk_p : process
begin
clk <= '0';
wait for 1 us;
clk <= '1';
wait for 1 us;
end process clk_p;
reset_p : process
begin
reset_n <= '0';
wait for 15500 ns;
reset_n <= '1';
wait;
end process reset_p;
incr_p : process
begin
inc <= '1';
wait for 25100 ns;
for i in 0 to 100 loop
inc <= '0';
wait for 20 us;
inc <= '1';
wait for 20 us;
end loop;
end process incr_p;
switch <= "0000000000";
end; -- architecture