code_fuer_die_abstimmungsschaltung [Digitale Elektronik und Technische Informatik]

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=== Code für die Abstimmungsschaltung ===

<code vhdl cntsw.vhd>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Count the number of switches
-- This is done in a direct lookup table

entity cntsw is 
  port (
    switch_i:   in std_ulogic_vector(4 downto 0);
    cnt_o:      out unsigned(2 downto 0)
  );
end; 

architecture rtl of cntsw is
begin

  process(switch_i)
  begin
    -- here we go...
  end process; 			   
end; -- architecture

</code>

<code vhdl decide.vhd>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Add the counted switches from both switch decoders
-- and decide if the led should switch on. 

entity decide is 
  port (
    swcnt1_i:   in unsigned(2 downto 0);
    swcnt2_i:   in unsigned(2 downto 0);
    sum_o:    out unsigned(3 downto 0);
    led_o:    out std_logic
  );
end; 

architecture rtl of decide is 
begin
  
			   
end; -- architecture

</code>


<code vhdl top.vhd>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is 
  port (
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
  );
end; 

architecture struct of top is

  component bin2seg is 
    port (
      number_i:       in  unsigned(3 downto 0);
      seg_o:          out std_ulogic_vector(6 downto 0)
    );
  end component;

  component cntsw is 
    port (
      switch_i:       in  std_ulogic_vector(4 downto 0);
      cnt_o:          out unsigned(2 downto 0)
    );
  end component;

  component decide is
    port (
      swcnt1_i :       in  unsigned(2 downto 0);
      swcnt2_i :       in  unsigned(2 downto 0); 
      sum_o  :         out unsigned(3 downto 0);
      led_o  :         out std_logic);
  end component; 

  signal swcnt1, swcnt2 : unsigned(2 downto 0);
  signal sum            : unsigned(3 downto 0);

begin
     
  cntsw_i0 : cntsw
    port map (
      switch_i => 
      cnt_o    => 
      );

  cntsw_i1 : cntsw
    port map (
      switch_i => 
      cnt_o    => 
      );

--  decide_i0 : decide
--    port map (
--      swcnt1_i => 
--      swcnt2_i => 
--      sum_o    => 
--      led_o    => LEDR(0));
      
  LEDR(9 downto 1) <= "000000000";
			   
end; -- architecture



</code>