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--- dt-code [2024/03/11 23:42]
beckmanf Cleanup - just entity, architecture and instantiation
+++ dt-code [2024/03/12 00:19] (current)
beckmanf add signal
@@ Line 29: / Line 29: @@
 Figure 1: Block and_gate with a_i and b_i as inputs and y_o as output
-Figure 1 shows the block "and_gate" with the inputs and outputs. This represents the entity. The entity code does not imply any functionality. The name "and_gate" is an identifier, i.e. it does not imply that this block actually works as an and gate. The architecture with the name "rtl" describes the implementation. Here it is a signal assignment with a boolean expression using the and function. This makes this circuit behave like an AND gate.
+Figure 1 shows the block "and_gate" with the inputs and outputs. This represents the entity. The entity code does not imply any functionality. The name "and_gate" is an identifier, i.e. it does not imply that this block actually works as an and gate.
-As the AND function can be described in one line of code, this block "and_gate" does not make too much sense, but it explains the idea of entity and architecture.
+<html>
+<img src="http://breakout.hs-augsburg.de/dwimg/and_gate_arch.svg" width="300" >
+</html>
+Figure 2: Architecture of "and_gate" which just contains and AND gate.
+The architecture with the name "rtl" describes the implementation. Here it is a signal assignment with a boolean expression using the and function. This makes this circuit behave like an AND gate. Figure 2 shows the schematic with the AND gate. As the AND function can be described in one line of code, this block "and_gate" does not make too much sense, but it explains the idea of entity and architecture.
 ===== Instantiation and hierarchical design =====
@@ Line 42: / Line 48: @@
 </html>
-Figure 2: "mux" block with a_i, b_i and s_i inputs and y_o output
+Figure 3: "mux" block with a_i, b_i and s_i inputs and y_o output
-Figure 2 shows the block interface of a circuit "mux" which has three inputs a_i, b_i and s_i and an output y_o.
+Figure 3 shows the block interface of a circuit "mux" which has three inputs a_i, b_i and s_i and an output y_o.
 This "mux"  is composed of two instances of "and_gate", an "or_gate" and an "inv_gate".
-Assume that we have defined not only the "and_gate" but also an "or_gate" and an "inv_gate". The mux circuit shall be composed of the xxx_gate subcircuits as shown in figure 3.
+Assume that we have defined not only the "and_gate" but also an "or_gate" and an "inv_gate". The mux circuit shall be composed of the xxx_gate subcircuits as shown in figure 4.
 <html>
-<img src="http://breakout.hs-augsburg.de/dwimg/mux-vhdl.svg" width="600" >
+<img src="http://breakout.hs-augsburg.de/dwimg/mux-vhdl.svg" width="800" >
 </html>
-Figure 3: Schematic of a multiplexer using inverter, and and or gates.
+Figure 4: Schematic of "mux"
-Figure 3 shows a schematic of a multiplexer using and_gate, or_gate and the inv_gate. The corresponding VHDL code is shown in listing 2.
+Figure 4 shows a schematic of a multiplexer using and_gate, or_gate and the inv_gate. The corresponding VHDL code is shown in listing 2.
 <code vhdl>
@@ Line 104: / Line 110: @@
 Listing 2: Structural VHDL code that instantiates and_gate, or_gate and inv_gate
-Note the signals s1, s2 and s3 which work as internal nets in "mux". The instantiation code introduces the name of the instance. In this example the names of the "and_gate" instances are "and_gate_i0" and "and_gate_i1". The instantiation code instantiates "work.and_gate" which means that there is a component "and_gate" assumed to be in library "work". The "and_gate" component is created in the work library when the corresponding vhdl code that defines the "and_gate" is compiled.
+The instantiation code introduces the name of the instance. In this example the names of the "and_gate" instances are "and_gate_i0" and "and_gate_i1". The instantiation code instantiates "work.and_gate" which means that there is a component "and_gate" assumed to be in library "work". The "and_gate" component is created in the work library when the corresponding vhdl code that defines the "and_gate" is compiled.
+===== Signals =====
+Note the signals s1, s2 and s3 in listing 2 which work as internal nets in "mux". But it is also possible to assign the value of an input port to a signal. The value of a signal can also be assign to an output port.
+Signals are defined between "architecture" and the following "begin".
 ===== Multiplexer Code - the real thing =====
-The previous code example in listing 2 and listing 1 show the hierarchical design of a multiplexer. Nobody would ever do it like that - it only serves as an example for hierarchical design which is used when the subcircuits have some complexity. The multiplexer function as described in listing 2 can be written in one line of code in VHDL. Here the full code showing that the complete mux block with entity and architecture. The function inside the architecture is only one line of code.
+The previous code example in listing 2 and listing 1 show the hierarchical design of a multiplexer. Nobody would ever do it like that - it only serves as an example for hierarchical design which is used when the subcircuits have some complexity. The multiplexer function as described in listing 2 can be written in one line of code in VHDL. Listing 3 shows the full code of "mux" with entity and architecture. The function inside the architecture is only one line of code.
 <code vhdl>