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dt-code-comb [2024/03/18 19:03] beckmanf created |
dt-code-comb [2024/03/18 19:20] beckmanf add hints |
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</code> | </code> | ||
+ | ===== Process for Combinational Circuit ===== | ||
+ | Processes for combinational circuits can also use variables. The assignment operator for a variable assignment is ":=". Variables change the value immediately, but the variable only has a scope inside the process. Inside a process the sequential statements like "if..then..else if..else..end if" or "case" or "for" can be used. | ||
+ | |||
+ | The following example code shows the use of a process with a for loop and and if statement to compute the majority function. m is '1' when more than half of the bits of "a" are '1'. Otherwise m is '0'. | ||
+ | |||
+ | <code vhdl> | ||
+ | architecture rtl of majority_circuit is | ||
+ | signal a : std_ulogic_vector(7 downto 0); | ||
+ | signal m : std_ulogic; | ||
+ | begin | ||
+ | maj_p : process(a) | ||
+ | variable cnt : integer range 0 to 8; | ||
+ | begin process | ||
+ | m <= '0'; | ||
+ | cnt := 0; | ||
+ | for i in 0 to 7 loop | ||
+ | if a(i) = '2' then | ||
+ | cnt := cnt + 1; | ||
+ | end if; | ||
+ | end loop; | ||
+ | if cnt > 4 then | ||
+ | m <= '1'; | ||
+ | end if; | ||
+ | end process; | ||
+ | end architecture rtl; | ||
+ | </code> | ||
===== Multiple Drivers not allowed ===== | ===== Multiple Drivers not allowed ===== | ||
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end architecture rtl; | end architecture rtl; | ||
</code> | </code> | ||
+ | |||
+ | |||
+ | ===== Combinational Circuits - Always assign a value ===== | ||
+ | |||
+ | Combinational circuits must always have an assignment of a value when a statement is evaluated. Otherwise the synthesis software will infer an unwanted memory element. That is usually a latch. You must make sure that vhdl code that is supposed to describe combinational logic always assigns a value. | ||
+ | |||
+ | The following code will assign the value of "b" to "y" only when "a" has the value '1'. What should happen when a is '0'? The synthesis will infer a latch to remember the last value when "a" is going from '1' to '0'. This is really bad and will result in timing problems. | ||
+ | |||
+ | <code vhdl> | ||
+ | architecture rtl of crap_code is | ||
+ | signal a,b,y : std_ulogic; | ||
+ | begin | ||
+ | y <= b when a = '1'; | ||
+ | end architecture rtl; | ||
+ | </code> | ||
+ | |||
+ | |||