library ieee;
use ieee.std_logic_1164.all;
 
entity shiftreg is 
  port (
    clk:               in  std_ulogic;
    reset_ni:          in  std_ulogic;
    load_i:            in  std_ulogic;
    shift_right_i:     in  std_ulogic;
    shift_left_i:      in  std_ulogic;
    rotate_left_by2_i: in  std_ulogic;  -- "11111000" -> "11100011"
    data_i:            in  std_ulogic_vector(7 downto 0);
    ser_o:             out std_ulogic   
  );
end; 
 
architecture rtl of shiftreg is
  signal sr     : std_ulogic_vector(7 downto 0);
  signal new_sr : std_ulogic_vector(7 downto 0);
begin 
  seq_p : process (clk_i, reset_ni)
  begin
    if reset_ni = '0' then
      sr <= "00000000";
    elsif rising_edge(clk_i) then 
      sr <= new_sr; 
    end if; 
  end process seq_p;  
 
  comb_p : process(load_i, sr)
  begin
    new_sr <= sr;
    if load_i = '1' then
      sr <= data_i
    elsif shift_right_i = '1' then
      new_sr(7) <= '0';
      new_sr(6 downto 0) <= sr(7 downto 1);
    elsif shift_left_i = '1' then
      new_sr <= sr(6 downto 0) & '0';
    elsif rotate_left_by2_i = '1' then
      new_sr <= sr(5 downto 0) & sr(7 downto 6);
    end if; 
  end process comb_p;
 
end architecture;