Volksmikro

Hubert Högl, < Hubert.Hoegl@fh-augsburg.de >
Revision 0.6

Source: proj/volksmikro/concept/concept.tex

1 Requirements
2 Design of the VM Board
    2.1 FT2232
    2.2 FPGA
    2.3 RS-232 Interface
    2.4 AVR Mega32
    2.5 JTAG Header (20-pin)
    2.6 Voltage Regulators
    2.7 Reset Logic
    2.8 The ARM7 Module
3 More Information
A Philips ARM7TDMI-S Controller
    A.1 LPC2129
    A.2 LPC2290
    A.3 LPC2292
B Commercial Boards using the LPC2xxx
    B.1 TinyARM
    B.2 Olimex LPC-H2129
    B.3 Phytec
    B.4 Tiniarm and Usbstamp by MPELTD
    B.5 Burntec TinyARM
    B.6 Armkey

1 Requirements

Here are a few requirements for the future Volksmikro Board:

Use an ARM Controller without MMU and with embedded flash memory (e.g. 256K). The main candidate is a cheap ARM7TDMI running at about 30 to 60 MHz clock speed.
Add about 512K SRAM. Some ARM7TDMI devices have a DRAM controllers (e.g. the OKI 67Q4002), other have only a SRAM interface (e.g. the Philips LPC2xxx and the Atmel SmartARM controllers). The Linux-variant running on MMU-less controllers - called uClinux - needs at least 4 to 8 MByte RAM to run. This amount can only be reasonably implemented using DRAMs. Thus with 512K SRAM we will ,,only'' be able to run non-linux OSs, e.g. eCos and uC/OS-II.
Serial Flash-Memory with e.g. 4 to 64 MBit to hold programs and data. Atmel calls them ,,Data Flash''). They interface to the SPI bus and have a very high clock speed of up to 30 MHz. It is also possible to use Multimedia- (MMC) or SecureDigital Cards (SD).
Serial EEPROM
Infrared Transmitter and Receiver to enable wireless upload of program and data.
CAN Controller. Many of the smart new ARM7TDMI controllers have one to four CAN interfaces built-in.
Real Time Clock with backup battery.
Connector for small ASCII and graphics LCD Displays. Typical controllers of these displays are:
- HD44780 (alphanumerical, 2x16, 2x20, 4x16, 4x20, etc.)
- T6963C (e.g. 240 x 128)
- SED1335, S1D13305 (up to 640 x 256 pixel)
CPLD as flexible glue logic between board components
CPLD or FPGA reserved for user functionality
Reset Logic
ARM7TDMI debugging over JTAG port, which is accessible over the USB bus or over a separate 20-pin header (use jumpers to select which one). Use a USB function interface implemented with a FTDIChip FT2232 device.
Add voltage regulators for all necessary voltages on the VM board. Most ARM controllers use two voltages, 2.5V for the core and 3.3V for the I/O pins. Both shall be generated from a single 5V supply by an integrated voltage converter, e.g. a MAX1626 or MAX1627 or similar device.
Must be able to feed supply voltage by (a) an external connector, or (b) by the USB bus.
For developing programs the GNU Tools will be used.
- GNU Toolchain (Compiler, Assembler, Linker, Binutils)
- GNU Debugger gdb - talks to the ARM7TDMI JTAG via USB!
- Bootloader to initialize FLASH, EEPROM and RAM
The tools shall be ready to use on a CDROM bundled with the Volksmikro. An adapted Knoppix CDROM could be used for this purpose.
It shall be possible to connect an Ethernet controller, e.g. a CS8900.
Need about 16 to 20 GPIO pins to connect LEDs (6) and a small keyboard matrix (10). Consider that most GPIO pins of the ARM7TDMI can not be used because they are already in use for the external bus interface. A possible solution would be to use the CPLD or a I2C-to-GPIO expander, e.g. the Philips PCA9555, or an Atmel AVR programmed to do the same task.

2 Design of the VM Board

Fig. 1 shows my first attempt (Summer 2003) to define the components which would be nice to have on the Volksmikro board. As you see, I wanted to have all components on a single board. Connectors on both sides with high pin-counts should make the MCU expansion bus available in the target system.

Fig. 1: [img/board.jpg]

Currently I dropped the idea to have all parts on a single board. I now much more like the idea to have a universal base board which can be combined with a variety of controller modules. The infrastructure of the base board can thus be reused also for other projects. An attempt to define the components on the base board can be seen in figure 2.

Fig. 2: [img/vm-kit.jpg]

Following are some ideas for the base board (a nice nickname would be ,,USBLab''):

The prototyping area should be large enough to hold an AVR Butterfly. This tiny and cheap AVR board can be programmed via an RS-232 link. Because the Butterfly already contains RS-232 level shifters, the Volksmikro base board must also provide true RS-232 signals over the FTDI chip, in addition to the 0V/5V UART signals. One should also care about the maximum supply voltage of the Butterfly which is 4.5V (DataFlash!).
It must be possible to program the on-board AVR and an optional AVR added to the prototyping area in serial programming mode (MISO, MOSI, CLK) via the FTDI 2232. For the uisp Programmer a patch exists to program over a FTDI 2232 device.
For the data exchange between PC and AVR the AVRPIPE software by Anatolij Gustschin (agust7@web.de) could be used.
Would like to have traditional connectors for AVR programming and CPLD configuration on the board.
For low-cost applications with use only the on-board AVR, the second CPLD is not needed.
The larger glue CPLD could also be an FPGA device, similar to the ,,Morph-IC'' by FTDI (http://www.morph-ic.com). The Morph-IC uses an Altera Acex EP1K10TC100-3.
The JTAG interfaces of the JTAG-enabled devices must be driven by the FTDI 2232. It is probably not a good idea to link them to a single chain, because debuggers for some devices (I think Atmel AVR) expect, that the tested device is the only device in the chain.
XXX add more

2005-02-12

Fig. 3: [img/vmschema.fig]

The following board configurations come to my mind:

FT2232 / Acex / Acex Expansion Connector
The board can be used for experiments with the Acex FPGA.
FT2232 / Acex / Mega32 AVR
The board can be used for experiments with the Atmel AVR and the Acex FPGA. The AVR is able to access the MMC card. Debugging of the AVR can be accomplished with an external JTAGICE, or by controlling the AVR JTAG port with the FT2232 (Channel-A, MPSSE). Serial port data can be accessed over USB.
FT2232 / Acex / ARM Module
The ARM Module is fully accessable over the USB port. JTAG debugging is possible over FT2232/Channel-A. Boot data (UART0) can be provided over USB Channel-B. UART1 can be routed to the DSub-9 connector to connect to a PC terminal program.
FT2232 / Acex / Mega32 AVR / ARM Module
The AVR drives UART0 of the LPC2292 for booting. The AVR reads boot data from the MMC card.

2.1 FT2232

Both channels A and B are connected to the FPGA. Channel A will mainly be used as a fast synchronous serial interface for JTAG and SPI. Channel B will be used as an asynchronous serial interface (RS-232).

Our goal is to be able to support the following operations over one USB connection:

Power supply
Reset the AVR and ARM7 targets
Configure the FPGA
AVR serial programming (MISO, MOSI, SCK)
Drive the UART port of the AVR
Drive the UART port of the ARM7 (console)
Drive the UART0 port of the ARM7 (booting)
Drive the JTAG debug port of the ARM7 for programming and debugging
Drive the JTAG debug port of the AVR for programming and debugging
Adjust the voltage regulators
Adjust the FPGA clock generator (e.g. DS1073, CY22150 or CY22393)
JTAG/Boundary Scan for the FPGA

2.2 FPGA

We will use an Altera Acex EP1K10-100/TQFP100. This device is also part of the FTDIchip ,,Morph'' Board.

XXX To Do

- Need a programmable clock generator, e.g. the DS1073 or the Cypres CY22150. The Dallas device is programmable by a single I/O pin whereas the Cypress device has an I2C interface.

        DS1073                        CY22150

  I/O   1    8 VCC              XIN  1    16  XOUT
  OUT0  2    7 XTAL             VDD  2    15  CLK6
  VCC   3    6 OE              AVDD  3    14  CLK5
  GND   4    5 /PDN/SELX       SDAT  4    13  VSS
                               AVSS  5    12  LCLK4
                               VSSL  6    11  VDDL
                              LCLK1  7    10  SCLK
                              LCLK2  8     9  LCLK3

- The Altera Acex is configured in passive serial mode (,,PS''), MSEL0 and MSEL1 are held low.

- The configuration bitstream for the Acex EP1K10 is 159160 bits large, which are 19895 bytes.

- Also add an enhanced configuration device EPC1 or EPC2 to configure the FPGA without a USB connection.

                        nCS   1   8  VCC
   serial data output   DATA  2   7  VCC
                        VCC   3   6  DCLK serial clock
                        GND   4   5  ASDI active serial data input

    Config Mem  ---- FPGA

    DATA             DATA0
    DCLK             DCLK
    ASDI             ASDO
    nCS              nCS0

The Morph board utilizes PS mode driven by FT2232 for configuring the FPGA. I think it is better to use the JTAG mode driven by the FT2232. It should also be possible to configure the FPGA over a serial configuration device (see fig. 4). The configuration device shall be programmed by the Altera download cable.

Fig. 4: Image taken from Altera Configuration Handbook, Chapter 4. [img/acex-config.jpg]

XXX To do: read SRunner: An Embedded Solution for Serial Configuration Device Programming White Paper and source code from Altera page.

- Programmable FPGA clock generator vs. fixed frequency. A DS1073 could be used for this job.

- How to combine configuration and JTAG. Note that the TQFP100 package doesn't have a TRST signal (tap reset).

- FPGA I/O voltage and target voltage of Mega32 and ARM7 must match. This will probably be 3.3 Volt.

2.3 RS-232 Interface

XXX To Do

2.4 AVR Mega32

XXX To Do

The JTAGICE connector is shown in figure 5.

Fig. 5: [img/avriceconn.fig]

The new JTAGICE mkII features the debugWIRE single-line debug interface. The devices with a debugWIRE interface have a 6-pin target connector ,,ISP6PIN'':

     MISO   1   2   VCC
     SCK    3   4   MOSI
     RESET  5   6   GND

These devices do not have a JTAG interface. The debugWIRE signal is connected to RESET pin of the AVR device. The following devices currently (2005-02-12) have debugWire: ATtiny13, ATtiny2313, ATmega48, ATmega88, ATmega168. All other JTAG-enabled devices like the ATmega16/32/64/128, ATmega162, ATmega169, ATmega323 have a 10-pin target header compatible to the old (mkI) JTAGICE.

Lit.: JTAGICE mkII Quick Start Guide (4 pages).

2.5 JTAG Header (20-pin)

See figure 6.

Fig. 6: [img/jtagconn.fig]

XXX To Do

2.6 Voltage Regulators

The MC33701 looks promising. It operates with 2.8 to 6 V input voltage and provides two I2C-programmable output voltages, e.g. for core and I/O voltage. Both output voltages range is between 0.8 and 5 V. Additional features are up/down power sequencing, power-on delay, overcurrent protection, reset output, watchdog timer.

XXX To Do

2.7 Reset Logic

MCP120

XXX To Do

2.8 The ARM7 Module

A controller module block diagram featuring the Philips LPC2xxx is shown in figure 7.

Fig. 7: [img/lpc2xxx-module.jpg]

RAM
In the production environment, most applications can run without external RAM. The internal 16 KByte SRAM should be enough for variables and stack/heap space. The application program will be in internal Flash memory. I do not expect typical applications running on a small operating system like mt, uC/OS-II or eCos to become larger than 256 KByte.

For debugging, the application program has to be run from RAM. Therefore we need at least a 256 KByte SRAM device, better would be a 512 KByte device.

In the case that a large operating system like uClinux is used, we need at least 4 MByte of RAM. Using Static-RAM we would need more than one chip. To save space it would be better to use Dynamic-RAM, but this implies that the controller has a built in (S)DRAM controller, e.g. like the Oki ML67Q4002.

Typical SRAM devices are:

Samsung K6F1616T6B Family (1M x 16 Super Low Power, 48-TSOP1, 3.3V, 55/70 ns, Standby 5uA, Operating 5mA)

Fig. 8: k6f1616t6b.jpg
Samsung K6X4008T1F Family (512K x 8, 3.3V, Standby 10uA, Operating 25 mA, 32-SOP, 55/70 ns, 32-TSOP2 or reverse)

Fig. 9: k6x4008t1f.jpg
Samsung K6X8016T3B Family (256K x 16, 3.3V, Standby 15uA, Operating 30mA, 44-TSOP2)

Fig. 10: k6x8016t3b.jpg
Samsung K6R4016V1C (256K x 16, 3.3V, 8/10 nsec, operating ca. 65 mA max, standby 20 mA) [Tip von Bernhard, bei Schukat, 2004-08-18]
Cypress asynchronous SRAM CY7C1061AV33 (1M x 16, 3.3V, operating 270mA, Standby 50mA, High-speed 8, 10, 12 ns)
Cypress asynchronous SRAM CY7C1062AV25 (512K x 32, 3.3V, operating 270mA, Standby 50mA, High-speed 8, 10, 12 ns)
Consider to use a Pseudostatic RAM when running a large operating system like uClinux.

Nonvolatile mass storage
A Multimedia Card (MMC) can be connected to one of the two SPI interfaces. A more intelligent circuit could boot from the MMC card, if the synchronous data from the card are converted to asynchronous data for UART0. The conversion could be done by e.g. a small Atmel AVR controller.

Fig. 11: Figure (a) adds a MMC card to the SPI interface. In figure (b) it is possible to access the MMC card as in (a), but moreover it allows to boot the LPC2xxx from the MMC card. The possible SWITCH datapaths are X1-B (boot from UART0), X2-W (R/W from/to MMC) and X1-W (boot from MMC).

Download and Debugging

Connecting the Host PC via serial port

The LPC2290 features a serial boot-loader (ISP - ,,In System Programming'') using UART0 which can be used for in-system download to RAM, flash programming and other useful tasks. The commands are sent in ASCII coding, following is the ISP command table:

Unlock
Set Baud Rate
Echo 
Write to RAM
Read Memory
Prepare sector(s) for write operation (+)
Copy RAM to Flash (+)
Go
Erase sector(s)  (+)
Blank check sector(s)  (+)
Read Part ID   (+)
Read Boot code version   (+)
Compare   (+)

Some of the commands can be called from within the application (IAP - ,,In Application Programming''). See the above commands marked with (+).

Booting can also be accomplished with the boot monitor RedBoot which is part of the eCos operating system. RedBoot is an open-source software package and is used to boot lots of embedded systems. It is ported to many different controller types and comprises a powerful monitor program and a gdb remote-stub implementation.

Connecting the Host PC via JTAG

I would like to have two types of connectivity for the ARM7TDMI JTAG port.

Standard 20-pin IDC header
USB (FT2232 function controller device)

Fig. 12 shows the 20-pin JTAG connector.

Fig. 12: The 20-pin JTAG connector.

There are different ways how to control the JTAG signals of the ARM7TDMI. At least the following come to my mind:

,,Wiggler'' and ,,Raven'' (both by Macraigor, http://www.macraigor.com).

The Wiggler is the cheapest way to connect a JTAG port to a PC. It is based on a simple (free) schematic with a 74LS244 connected to the PC parallel port. The speed is about 16 kbit/s.

Following is the Wiggler schematic. It is plugged into the PC parallel port with a SubD-25 connector. On the right side is a 20-pin connector, which feeds the JTAG port shown in figure 6.

PL1 25wayD Male                                                 PL2 20wayIDC

PL1/17-25 <--------------+-------------------------+--+-----------<  PL2/4,6,8,
                         |                         |  |              10,12,14,
                         |    AC244          200nF =  = 4.7uF        16,18,20
                         | +------------+  Vcc     |  |
         TDI          0v +-| 1       20 |-+--------+--+-----------<  PL2/1,2
PL1/5  >-------------------| 2       19 |-+
         TMS               | 3       18 |-----XXXX---------------->  PL2/5
PL1/3  >-------------------| 4       17 |     51R     
         TCLK              | 5       16 |-----XXXX---------------->  PL2/7
PL1/4  >-------------------| 6       15 |     51R
                           | 7       14 |-----XXXX---------------->  PL2/9
                      +----| 8       13 |     51R
                      |    | 9       12 |-----XXXX---+
                      |  +-| 10      11 |     51R    |
                      |  | +------------+            |
                      |  V 0v                        |
                      +------------------------------------------<   PL2/13
         TDO                                         |
PL1/11 <---------------------------------------------+


                            DTC114   /-------xxxx----------------<   PL2/15
         RST            10k       | /        51R
PL1/2  >----------------XXXX--+---|<
                              |   | \
                              X      V
                         47k  X      |  
                              X      |
                              |      |
                              V 0v   V

The Raven is another parallel port dongle to drive the JTAG signals. It is more powerful than the Wiggler, because it uses a CPLD to serialize the JTAG data. The speed is about 64 kbit/s. The schematic of the Raven is not publicly available. The original Raven by Macraigor is rather expensive. Amontec (http://www.amontec.com) offers the Chameleon POD, which can be made compatible to the Raven. This works by downloading a specific configuration bitstream to the internal Xilinx CPLD. Beside the Raven, Chameleon is able to emulate all well known dongles, e.g. Xilinx, Altera, Wiggler, and many others.

Macraigor offers software to control an ARM7 (and others) JTAG port with the GNU debugger gdb. The Wiggler is supported only by the MS-Windows version of OCDLibRemote. The Raven is supported by the Linux and MS-Windows version of OCDLibRemote. OCDLibRemote contains a server, which allows to connect gdb by the remote debug protocol, the gdb target is target remote localhost:8888. The bad news is that OCDLibRemote is only available as a binary package.

Another way to control an ARM7TDMI by JTAG is given by the ARMTOOL, contained in Midori Linux http://home.at/cgi-bin/viewcvs.cgi/midori/sources/armtool/. This approach does not depend on the OCDLibRemote library.
From the JTAG FAQ:

,,ARMTOOL is a very simple JTAG monitor that supports upload and download a binary image into memory and its execution. ARMTOOL is ARM7TDMI specific (some part of code is derived from GDBICE project), but may work with some of ARM9 cores (to be tested). Current version supports JTAG adapters compatible with Macraigor Wiggler, Altera ByteBlasterMV and Xilinx Parallel port JTAG adapter.''
EPI Tools (http://www.epitools.com) JTAG Box ,,Jeenie''. This box converts RDI commands (a.k.a. Angel Debug Protocol) to JTAG commands. The corresponding GDB target thus is target rdi. The Jeenie Box costs about 1500 Euro and contains an ARM710 with JTAG-specific firmware.
BDI2000 Debugger. This is a rather expensive (ca. 2000 Euro) external box to control the JTAG port. It has the advantage to connect the debugger over a TCP/IP network. The URL of the manufacturer is http://www.abatron.ch.
Homebuilt USB-to-JTAG converter, e.g. with chips from FTDI (FT2232C or similar, http://www.ftdichip.com) or Cypress (AN2131 or similar). It would be nice to do all the following over a simple USB interface:
- Power supply
- Drive UART0 Debug Channel
- Drive JTAG Port
- Program the on-board CPLD/FPGA
- Do general-purpose I/O
See the ,,Jelie'' project (http://lapwww.epfl.ch/dev/arm/jelie/) for a similar approach.

Operating Systems
All of the following real time operating systems are freely available under an open source license:

XMK (,,Extreme Minimal Kernel'', http://www.shift-right.com/xmk/)
uC/OS, uC/OS-II (www.ucos-ii.com)
FreeRTOS (http://www.freertos.org)
eCos (http://sources.redhat.com/ecos/), with ELIX API.
uClinux (http://www.uclinux.org)

Be aware that the above RTOSes are rather small - except uClinux. For uClinux a minimum amount of 4 to 8 MByte of external (D)RAM is necessary. For all others a 128 kbyte to 512 kbyte memory (SRAM) are sufficient.

Development Tools
All development tools are available both for Linux and MS-Windows. They can be downloaded from the GNUARM Website, http://www.gnuarm.com.

Another source for the GNU Toolchain is http://www.macraigor.com/full_gnu.htm.

3 More Information

- Philips Semiconductor Homepage
http://www.semiconductors.philips.com

- Philips MCU discussion forum
http://forums.semiconductors.philips.com/forums/viewforum.php?f=1

- ARMuC Wiki
http://www.open-research.org.uk/ARMuC/

- LPC2XXX Yahoo Newsgroup
http://groups.yahoo.com/group/lpc2000/

- Heyrick's ARM Assembler Tutorial (Richard Murray)
http://www.heyrick.co.uk/assembler

- ARM code tutorial
http://www.soup-kitchen.net/armcode/

- LPC210x ARM7 Microcontroller Tutorial (enz-at-dreamislife-dot-com)
http://www.dreamislife.com/arm/

- GBA Assembler Tutorial
http://www.robsite.de/daten/tutorials/devgba/gba_asm1.html

- Leon Heller's LPC210x Prototyping System
http://www.geocities.com/leon_heller/lpc2104.html

- Peter Y. K. Cheung, Introduction to Computer Systems (Imperial College, London)
http://www.ee.ic.ac.uk/pcheung/teaching/ee2_computing/

- Newsgroup
comp.sys.arm

- Information about Philips LPC21xx ARM Microcontrollers
http://www.lpc2100.com/

- LPCTools
http://www.lpctools.com/

- Micrium Application Note AN-1229, ,,uC/OS-II and The Philips LPC2000 Series CPU'', 13 pages (AN-1229.zip). Darin ist enthalten: Micrium Application Note AN-1011A, ,,uC/OS-II and The ARM7 Processor'', 28 pages.

- Amitkumar Bhojraj, Philips Application Note AN10256, Using In-Application Programming (IAP) techniques for programming the on-chip Flash, 6 pages, 2003-12-12.

- Bill Gatliff, Getting Started With GNU (for ARM Evaluator-7T, but can also be applied to Philips ARM)
http://billgatliff.com/articles/gnu-cci/

- Newmicros USB to JTAG Cable, http://www.mpeltd.demon.co.uk/usbstamp.htm. Contains the components LPC2106, 24C512 EEPROM, XC2C32/64 to drive the JTAG Port connected to the target system, FT245 with AT93C64A, MAX3222. Schematic available. [April 2004]

- http://arm.web7days.com

- ARM Instruction Set Quick Reference Card. XXX add link.

- LPC2290 datasheet (no internal Flash, external bus interface, 2 x CAN) local: ../philips/LPC2290-01.pdf

Literature for the ARM7TDMI core

- ARM7TDMI Product Overview, Arm Limited, 16 pages, ../arm/DVI0027B_7_R3.pdf

- ARM7TDMI (Rev. 4) Technical Reference Manual, Arm Limited, 2001, 294 Seiten, ../arm/DDI0210B_7TDMI_R4.pdf

- ARM Architecture Reference Manual, Arm Limited, 811 pages, ../arm/DDI0100E_ARM_ARM.pdf

- Instruction Set Quick References ../arm/QRC_ARM.pdf and ../arm/QRC_Thumb.pdf

- ARM7TDMI Debug Architecture, Arm Limited, 30 pages, ../arm/DAI0028A_arm7tdmi_debug.pdf

Literature for the Oki ML67Q4002 ARM7TDMI controller

- Oki uPlat Flyer about ARM-Based 32-Bit Controllers, 8 pages, local: ../oki/Oki-Flyer.pdf

- Overview for the ML674K series, 19 pages, February 2004, local: ../oki/674001DS-06.pdf

- 67Q4001/2/3 Overview, 24 pages, local: ../oki/ml674001_q4002_q4003.pdf

- ML674001/Q4002/Q4003 User's Manual, January 31 2004, 440 pages, local: ../oki/ML674001_Q4002_Q4003_Users_Manual.pdf

- Interfacing the ML87V3104 QVGA to SVGA LCD Controller and the ML674000 Microcontroller, August 2003, 19 pages, local: ../oki/armappnotelcd.pdf

- Oki Application Note JTAG Boundary Scan for 0.8 um and 0.5 um SOG and CSA Technologies, April 1995, 40 pages, local: ../oki/JTAG-Boundary-Scan.pdf

A Philips ARM7TDMI-S Controller

In June 2004 the most promising 32-bit processor with an ARM core to replace a 8- or 16-bit controller like the 68HC11 seems to be the Philips LPC2xxx series. The LPC2129 and LPC2290 each have two built in CAN interfaces, the first is without external bus interface (EBI), the second with EBI.

The LPC2129 would be ideal as a processor for productive use. When choosing an operating system as small as uC/OS or eCos, the built-in 256 kbyte Flash memory would be enough for small control applications. For use as a development system this processor is not ideal, because for every software test the internal Flash has to be reprogrammed.

For a development system the LPC2290 is a better choice. Programs to be tested can be run and debugged from an externally added SRAM with 512 KByte size.

The generic features of the LPC2129/LPC2290 are:

Two supply voltags 3.3 (I/O) and 1.8 (CPU) volt.
256 KByte on-chip Flash memory. Programming with (1) JTAG, (2) In System Programming and UART0 (ISP) and (3) In Application Programming (IAP)
60 MHz maximum CPU clock from PLL
16 kB on-chip SRAM
External bus interface (LPC2290): SRAM, ROM, Flash EPROM, Burst ROM
Built-in RTC with minutes, hours, day, month, year
Two CAN controllers
Two UARTs (16C550), UART0 (Tx/Rx), UART1 with standard modem control lines
I2C up to 400 kbit/s
76 GPIOs without external memory interface in use
Eight channel 10-bit ADC, > = 2.44 usec conversion time
PWM
Timer0 and Timer1, four 32-bit match registers
Two reduced power modes: Idle and Power-Down
Embedded Trace Macrocell using the 10 pins TRACECLK, PIPESTAT[2:0], TRACESYNC, TRACEPKT[3:0] and EXTIN[0]. These pins are multiplexed with P1.25-16. An external Trace Port Analyzer is needed to trace the execution of a program.
RealMonitor for realtime debugging preprogrammed in Flash
Two SPI interfaces
Watchdog

Fig. 13: Philips LPCxxxx products (part 1)

Fig. 14: Philips LPCxxxx products (part 2)

A.1 LPC2129

This device is without an external bus interface.

Fig. 15: LPC2129 Block Diagram

Fig. 16: LPC2129 Pins

A.2 LPC2290

This device has an external bus interface. The data bus is 32-bit wide and mapped on Port 2 (P2.0 - P2.31). The address bus is capable to address four banks with a maximum of 16 mbyte in each bank. The address signal A0 - A23 are on Port 3 P3.0 - P3.23. The chip select signals are on P1.0 (CS0), P3.26 (CS1), P3.25 (CS2) and PC.24 (CS3). Each bank may be 8/16/32 bits wide. Fig. 17 shows the block diagram of the LPC2290.

Fig. 17: LPC2290 Block Diagram

The pinout of the LPC2290 is shown in figure 18.

Fig. 18: LPC2290 Pins

A.3 LPC2292

Fig. 19: LPC2292 Block Diagram

The pinout of the LPC2292 is shown in figure 20.

Fig. 20: LPC2292 Pins

B Commercial Boards using the LPC2xxx

B.1 TinyARM

The TinyARM can be ordered from the Elektronikladen, http://www.elektronikladen.de. See figures 21 and 22.

Fig. 21: TinyARM Schematic

Fig. 22: TinyARM PCB

B.2 Olimex LPC-H2129

URL: http://www.olimex.com/dev. See figures 23, 24 and 25.

Fig. 23: Schematic of the Olimex LPC-H2129 Board.

Fig. 24: PCB Floor Plan of the Olimex LPC-H2129 Board.

Fig. 25: JTAG Connector of the Olimex LPC-H2129 Board.

Features:

LPC2129 (ARM7TDMI-S core), 10 MHz crystal, 76x55 mm, 5V tolerant I/O, 2x10 pin JTAG interface, 4-layer PCB
Two RS232 Channels
Reset Circuit (simple RC circuit)
Bootloader

The manual mentions that a 14.7456 MHz external crystal leads to non-functioning JTAG interface. Theoretically the external crystal can be 10 - 25 MHz. Therefore had to use a 10 MHz crystal, with the side effect that Philips ISP utility can only run 38400 baud. With 14.7456 MHz can run serial port up to 115 Kbps, but without JTAG use.

B.3 Phytec

The Phytec (http://www.phytec.de) phyCORE-LPC2292/94 is a board with an LPC2292/94 (TQFP-144) and some megabytes of external memory. The main features are 60 x 53 mm, two 100-pin Molex connectors, 1MB to 8 MB asynchronous RAM with 32-bit, 2MB to 16 MB asynchronous Flash with 32-bit, 10/100 MBit Ethernet Controller SMSC LAN91C111 with integrated PHY layer (optional), I2C Real Time Clock with internal quartz (RTC), 1K SPI EEPROM (Atmel AT25080, AT25160, etc.), CAN Transceiver Infineon TLE6250V33, DS2401 Silicon Serial Number, typical Flash Memory is 29LV800B, 29LV160B and 29LV320B (all 3.3V devices), MAX6301 Watchdog, max 60 MHz clock, not data bus buffers on board (but recommended for external hardware).

Fig. 26: Phytec phyCORE-LPC2292/94

B.4 Tiniarm and Usbstamp by MPELTD

This is a small module by Microprocessor Engineering Limited, http://www.mpeltd.demon.co.uk.

Fig. 27: Tiniarm by MPELTD [img/tiniarm.jpg]

Fig. 28: Usbstamp by MPELTD [img/usbstamp.jpg]

B.5 Burntec TinyARM

http://www.burntec.com/tinyarm.asp

B.6 Armkey

ARMKEY V1.00 is a DIL-40 module with LPC2104. They have an eForth to download. See http://www.egenom.com/product.htm.

Fig. 29: Armkey [img/ak100_3.jpg]

File translated from T_EX by T_TH, version 3.63.
On 13 Feb 2005, 21:47.

Volksmikro

Hubert Högl, < Hubert.Hoegl@fh-augsburg.de > Revision 0.6

Contents

1 Requirements

2 Design of the VM Board

2.1 FT2232

2.2 FPGA

2.3 RS-232 Interface

2.4 AVR Mega32

2.5 JTAG Header (20-pin)

2.6 Voltage Regulators

2.7 Reset Logic

2.8 The ARM7 Module

3 More Information

A Philips ARM7TDMI-S Controller

A.1 LPC2129

A.2 LPC2290

A.3 LPC2292

B Commercial Boards using the LPC2xxx

B.1 TinyARM

B.2 Olimex LPC-H2129

B.3 Phytec

B.4 Tiniarm and Usbstamp by MPELTD

B.5 Burntec TinyARM

B.6 Armkey

Hubert Högl, < Hubert.Hoegl@fh-augsburg.de >
Revision 0.6