library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is 
  port (
    SW:         in  std_ulogic_vector(3 downto 0); -- Switches
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0)
  );
end; 

architecture struct of top is

  component bin2seg is 
    port (
      number_i:       in  unsigned(3 downto 0);
      seg_o:          out std_ulogic_vector(6 downto 0)
    );
  end component;

begin
     
  bin2seg_i0 : bin2seg
    port map (
      number_i => unsigned(SW),
      seg_o    => HEX0);
      
  LEDR <= "0000000000";
                   			   
end; -- architecture