library ieee;
use ieee.std_logic_1164.all;

entity de1_and5 is
port ( SW   : in   std_ulogic_vector(9 downto 0);
       LEDR : out  std_ulogic_vector(1 downto 0));
end entity de1_and5;

architecture rtl of de1_and5 is
begin
end architecture rtl;