library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top is port ( SW: in std_ulogic_vector(9 downto 0); -- Switches KEY: in std_ulogic_vector(3 downto 0); -- Keys LEDR: out std_ulogic_vector(9 downto 0); -- Red LEDs above switches HEX0: out std_ulogic_vector(6 downto 0); -- 7 Segment Display HEX1: out std_ulogic_vector(6 downto 0); -- 7 Segment Display HEX2: out std_ulogic_vector(6 downto 0) -- 7 Segment Display ); end; architecture struct of top is component bin2seg is port ( number_i: in unsigned(3 downto 0); seg_o: out std_ulogic_vector(6 downto 0) ); end component; component counter is port ( clk_i: in std_ulogic; reset_ni: in std_ulogic; count_o: out unsigned(7 downto 0) ); end component; signal count : unsigned(7 downto 0); begin bin2seg_i0 : bin2seg port map ( number_i => count(3 downto 0), seg_o => HEX0); bin2seg_i1 : bin2seg port map ( number_i => count(7 downto 4), seg_o => HEX1); counter_i0 : counter port map ( clk_i => KEY(0), reset_ni => KEY(1), count_o => count); LEDR(7 downto 0) <= std_ulogic_vector(count); LEDR(9 downto 8) <= "00"; HEX2 <= "1111111"; end; -- architecture