library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- Edge detection circuit entity edge is port ( clk_i: in std_ulogic; reset_ni: in std_ulogic; key_i: in std_ulogic; rising_edge_o: out std_ulogic ); end; architecture rtl of edge is signal key_reg : std_ulogic; begin edge_detection_p : process(key_i, key_reg) begin -- Hier code einfuegen end process edge_detection_p; -- The sequential process for flipflop instantiation -- All signal assignments in this process will result in flipflops. key_reg_p : process (clk_i, reset_ni) begin if reset_ni = '0' then -- hier code einfuegen elsif rising_edge(clk_i) then -- hier code einfuegen end if; end process key_reg_p; end; -- architecture