library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Finite State Machine (FSM) for rising edge detection
-- The edge_o signal will go to "1", when there is a 01 sequence
-- at the key_i input. 

entity edge is 
  port (
    clk_i:            in std_ulogic;
    reset_ni:         in std_ulogic;
    key_i:            in std_ulogic;  
    edge_o:    out std_ulogic 
  );
end; 

architecture rtl of edge is  
  type state_type is (start_s, null_s, eins_s);
  signal current_state, next_state : state_type;
begin

  next_state_and_output_p : process(current_state, key_i)
  begin
    edge_o <= '0';
    next_state <= current_state; 
    case current_state is
      when start_s =>
        next_state <= null_s;
      when null_s  =>
        if key_i = '1' then
          next_state <= eins_s; 
        end if; 
      when eins_s  =>
        edge_o <= '1';
        next_state <= null_s; 
      when others => 
        next_state <= current_state; 
    end case; 
  end process next_state_and_output_p;  

  -- The sequential process for flipflop instantiation
  -- All signal assignments in this process will result in flipflops.
  state_reg_p : process (clk_i, reset_ni)
  begin
    if reset_ni = '0' then
      current_state <= start_s;
    elsif rising_edge(clk_i) then
      current_state <= next_state; 
    end if; 
  end process state_reg_p;      
 			   
end; -- architecture