library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is 
  port (
    CLOCK_50:   in  std_ulogic;                    -- 50 MHz Clock input
    GPIO_1:     in  std_ulogic_vector(35 downto 0);-- GPIO poins 
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
    KEY:        in  std_ulogic_vector(3 downto 0); -- Keys
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
  );
end; 

architecture struct of top is

  component bin2seg is 
    port (
      number_i:       in  unsigned(3 downto 0);
      seg_o:          out std_ulogic_vector(6 downto 0)
    );
  end component;

  component counter is 
    port (
      clk_i:          in  std_ulogic;
      reset_ni:       in  std_ulogic;
      enable_i:       in  std_ulogic; 
      up_i:           in  std_ulogic; 
      count_o:        out unsigned(7 downto 0)
    );
  end component;

  component qdec is
    port (
      clk_i:             in std_ulogic;
      reset_ni:          in std_ulogic;
      s1_i:              in std_ulogic;
      s2_i:              in std_ulogic; 
      rising_edge_s1_i:  in std_ulogic;
      rising_edge_s2_i:  in std_ulogic;
      falling_edge_s1_i: in std_ulogic;
      falling_edge_s2_i: in std_ulogic; 
      up_o:              out std_ulogic;
      enable_o:          out std_ulogic);
  end component; 

  component edge is 
    port (
      clk_i:          in  std_ulogic;
      reset_ni:       in  std_ulogic;
      key_i:          in  std_ulogic;
      falling_edge_o: out std_ulogic; 
      rising_edge_o:  out std_ulogic 
    );
  end component;
 
  signal count : unsigned(7 downto 0);
  signal enable, up : std_ulogic; 
  signal reset_n : std_ulogic;
  signal s1, s2 : std_ulogic;
  signal rising_edge_s1, falling_edge_s1 : std_ulogic;
  signal rising_edge_s2, falling_edge_s2 : std_ulogic; 

begin
       
  bin2seg_i0 : bin2seg
    port map (
      number_i => count(3 downto 0),
      seg_o    => HEX0);
      
  bin2seg_i1 : bin2seg
    port map (
      number_i => count(7 downto 4),
      seg_o    => HEX1);
          
  counter_i0 : counter
    port map (
      clk_i    => CLOCK_50,
      reset_ni => reset_n,
      enable_i => enable,
      up_i     => up,
      count_o  => count);

  edge_i0 : edge
    port map (
      clk_i         => CLOCK_50,
      reset_ni      => reset_n,
      key_i         => s1,
      rising_edge_o => rising_edge_s1,
      falling_edge_o => falling_edge_s1);

  edge_i1 : edge
    port map (
      clk_i         => CLOCK_50,
      reset_ni      => reset_n,
      key_i         => s2,
      rising_edge_o => rising_edge_s2,
      falling_edge_o => falling_edge_s2);
  
  qdec_i0 : qdec
    port map (
      clk_i             => CLOCK_50,
      reset_ni          => reset_n,
      s1_i              => s1,
      s2_i              => s2,
      rising_edge_s1_i  => rising_edge_s1,
      falling_edge_s1_i => falling_edge_s1,
      rising_edge_s2_i  => rising_edge_s2,
      falling_edge_s2_i => falling_edge_s2,
      up_o              => up,
      enable_o          => enable); 

  s1 <= GPIO_1(0);
  s2 <= GPIO_1(1); 
  reset_n <= KEY(0);
            
  LEDR(7 downto 0) <= std_ulogic_vector(count);
  LEDR(9 downto 8) <= GPIO_1(1 downto 0); 
  HEX2 <= "1111111";
			   
end; -- architecture