library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top_tb is end; architecture beh of top_tb is component top is port ( CLOCK_24: in std_ulogic_vector(1 downto 0); KEY: in std_ulogic_vector(3 downto 0); SW: in std_ulogic_vector(9 downto 0); I2C_SCLK: out std_ulogic; I2C_SDAT: inout std_ulogic; AUD_ADCLRCK: out std_ulogic; AUD_ADCDAT: in std_ulogic; AUD_DACLRCK: out std_ulogic; AUD_DACDAT: out std_ulogic; AUD_XCK: out std_ulogic; AUD_BCLK: out std_ulogic; LEDR: out std_ulogic_vector(9 downto 0); HEX0: out std_ulogic_vector(6 downto 0) ); end component; signal clk, reset_n : std_ulogic; signal switch, ledr : std_ulogic_vector(9 downto 0); signal hex : std_ulogic_vector(6 downto 0); signal i2c_clk, i2c_dat : std_ulogic; signal key : std_ulogic_vector(3 downto 0); signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic; signal clk24 : std_ulogic_vector(1 downto 0); begin top_i0 : top port map ( CLOCK_24 => clk24, KEY => key, SW => switch, I2C_SCLK => i2c_clk, I2C_SDAT => i2c_dat, AUD_ADCLRCK => aud_adclrck, AUD_ADCDAT => aud_adcdat, AUD_DACLRCK => aud_daclrck, AUD_DACDAT => aud_dacdat, AUD_XCK => aud_xck, AUD_BCLK => aud_bclk, LEDR => ledr, HEX0 => hex); clock_p : process begin clk <= '0'; wait for 21 ns; clk <= '1'; wait for 21 ns; end process clock_p; clk24(0) <= clk; reset_p : process begin reset_n <= '0'; wait for 15 us; reset_n <= '1'; wait; end process reset_p; key(0) <= reset_n; key(3 downto 1) <= "000"; switch <= "0000000000"; aud_adcdat <= '1'; end; -- architecture