library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- DAC (Digital to Analog Converter) Interface
-- Loads a word in parallel and shifts it out as serial bit stream
-- The data needs to be shifted out twice. This is required as 
-- the audio interface needs stereo data.

entity dacintf is 
  port (
    clk_i                  : in std_ulogic;
    reset_ni               : in std_ulogic;
    load_i                 : in std_ulogic; 
    data_i                 : in std_ulogic_vector(15 downto 0); 
    en_i                   : in std_ulogic; 
    ser_dat_o              : out std_ulogic);
end; 

architecture rtl of dacintf is

begin

  load_and_shift_p : process(clk_i, reset_ni)
  begin
    if reset_ni = '0' then
    elsif rising_edge(clk_i) then
    end if; 
  end process load_and_shift_p;
  
  ser_dat_o <= '0';
			   
end; -- architecture