library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ADC (Analog to Digital Converter) Interface
-- Shifts in 16 bits and provides the data in parallel
-- When all 16 bits are shifted in, the valid_o output is set to "1" for one clock cycle

entity adcintf is 
  port (
    clk_i                  : in std_ulogic;
    reset_ni               : in std_ulogic;
    en_i                   : in std_ulogic; 
    valid_o                : out std_ulogic; 
    data_o                 : out std_ulogic_vector(15 downto 0); 
    start_i                : in std_ulogic; 
    ser_dat_i              : in std_ulogic);
end; 

architecture rtl of adcintf is

begin

  seq_p : process(clk_i, reset_ni)
  begin
    if reset_ni = '0' then
    elsif rising_edge(clk_i) then
    end if; 
  end process seq_p;  

  statem_comb_p : process(start_i)
  begin
    valid_o <= '0';
  end process statem_comb_p;
  			   
end; -- architecture