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binaer_zu_7-segment_kodierer_code [2010/11/19 20:17] (current)
beckmanf created
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 +==== Binär zu 7-Segment Kodierer ====
  
 +<code vhdl bin2seg.vhd>​
 +library ieee;
 +use ieee.std_logic_1164.all;​
 +use ieee.numeric_std.all;​
 +
 +-- Translate a 4 Bit unsigned number to a 7-Segment Control
 +--           ​---0---
 +--           ​| ​    |
 +--           ​5 ​    1
 +--           ​| ​    |
 +--           ​---6---
 +--           ​| ​    |
 +--           ​4 ​    2
 +--           ​| ​    |
 +--           ​---3---
 +-- Display the correct number for 0 - 9 and E for all other 
 +-- numbers which can be coded with 4 Bits (10-15).  ​
 +
 +entity bin2seg is 
 +  port (
 +    number_i: ​  ​in ​ unsigned(3 downto 0);
 +    seg_o: ​     out std_ulogic_vector(6 downto 0)
 +  );
 +end; 
 +
 +architecture rtl of bin2seg is
 +begin
 +
 +  trans_p: process(number_i)
 +  begin
 +    case number_i is 
 +      when "​0000"​ => seg_o <= "​1000000";​
 +      when "​0001"​ => seg_o <= "​1111001";​
 +-- continue here...
 +      when others => seg_o <= "​0000110";​
 +    end case;
 +  end process;
 +    
 +end; -- architecture
 +
 +</​code> ​
 +
 +
 +<code vhdl top.vhd>
 +library ieee;
 +use ieee.std_logic_1164.all;​
 +use ieee.numeric_std.all;​
 +
 +entity top is 
 +  port (
 +    SW:         ​in ​ std_ulogic_vector(3 downto 0); -- Switches
 +    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
 +    HEX0:       out std_ulogic_vector(6 downto 0)
 +  );
 +end; 
 +
 +architecture struct of top is
 +
 +  component bin2seg is 
 +    port (
 +      number_i: ​      ​in ​ unsigned(3 downto 0);
 +      seg_o: ​         out std_ulogic_vector(6 downto 0)
 +    );
 +  end component;
 +
 +begin
 +     
 +  bin2seg_i0 : bin2seg
 +    port map (
 +      number_i => unsigned(SW),​
 +      seg_o    => HEX0);
 +      ​
 +  LEDR <= "​0000000000";​
 +                   ​  ​  
 +end; -- architecture
 +
 +</​code>​
 +
 +<code vhdl top_tb.vhd>​
 +library ieee;
 +use ieee.std_logic_1164.all;​
 +use ieee.numeric_std.all;​
 +
 +entity top_tb is
 +end; 
 +
 +architecture beh of top_tb is
 +
 +  component top
 +  port (
 +    SW:         ​in ​ std_ulogic_vector(3 downto 0); -- Switches
 +    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
 +    HEX0:       out std_ulogic_vector(6 downto 0) -- 7 Segment Display
 +    );
 +  end component;
 +
 +  signal number ​             : unsigned(3 downto 0);
 +  signal switch ​             : std_ulogic_vector(3 downto 0);
 +  signal hex0                : std_ulogic_vector(6 downto 0);
 +  signal ledr                : std_ulogic_vector(9 downto 0);
 +
 +begin
 +  ​
 +  top_i0 : top
 +    port map (
 +      SW                  => switch,
 +      LEDR                => ledr,
 +      HEX0                => hex0);
 +       
 +  switch <= std_ulogic_vector(number);​
 +  ​
 +  process
 +  begin
 +    number <= "​0000";​
 +    wait for 10 us; 
 +    for i in 0 to 31 loop
 +      number <= number + 1;
 +      wait for 10 us;
 +    end loop;  ​
 +  end process; ​
 +
 +end; -- architecture
 +</​code>​
  • binaer_zu_7-segment_kodierer_code.txt
  • Last modified: 2010/11/19 20:17
  • by beckmanf