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code_fuer_die_additionsschaltung [2010/11/19 21:51] beckmanf created |
code_fuer_die_additionsschaltung [2010/11/23 13:40] beckmanf top und top_tb eingefügt |
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end process add_p; | end process add_p; | ||
+ | end; -- architecture | ||
+ | |||
+ | </code> | ||
+ | |||
+ | <code vhdl top.vhd> | ||
+ | library ieee; | ||
+ | use ieee.std_logic_1164.all; | ||
+ | use ieee.numeric_std.all; | ||
+ | |||
+ | entity top is | ||
+ | port ( | ||
+ | SW: in std_ulogic_vector(9 downto 0); -- Switches | ||
+ | LEDR: out std_ulogic_vector(9 downto 0); -- Red LEDs above switches | ||
+ | HEX0: out std_ulogic_vector(6 downto 0); -- 7 Segment Display | ||
+ | HEX1: out std_ulogic_vector(6 downto 0); -- 7 Segment Display | ||
+ | HEX2: out std_ulogic_vector(6 downto 0) -- 7 Segment Display | ||
+ | ); | ||
+ | end; | ||
+ | |||
+ | architecture struct of top is | ||
+ | |||
+ | component bin2seg is | ||
+ | port ( | ||
+ | number_i: in unsigned(3 downto 0); | ||
+ | seg_o: out std_ulogic_vector(6 downto 0) | ||
+ | ); | ||
+ | end component; | ||
+ | |||
+ | component adder is | ||
+ | port ( | ||
+ | a_i: in unsigned(3 downto 0); | ||
+ | b_i: in unsigned(3 downto 0); | ||
+ | sum_o: out unsigned(3 downto 0) | ||
+ | ); | ||
+ | end component; | ||
+ | | ||
+ | signal a, b, sum : unsigned(3 downto 0); | ||
+ | | ||
+ | begin | ||
+ | | ||
+ | a <= unsigned(SW(3 downto 0)); | ||
+ | b <= unsigned(SW(8 downto 5)); | ||
+ | |||
+ | bin2seg_i0 : bin2seg | ||
+ | port map ( | ||
+ | number_i => a, | ||
+ | seg_o => HEX0); | ||
+ | | ||
+ | bin2seg_i1 : bin2seg | ||
+ | port map ( | ||
+ | number_i => b, | ||
+ | seg_o => HEX1); | ||
+ | | ||
+ | bin2seg_i2 : bin2seg | ||
+ | port map ( | ||
+ | number_i => sum, | ||
+ | seg_o => HEX2); | ||
+ | | ||
+ | adder_i0 : adder | ||
+ | port map( | ||
+ | a_i => a, | ||
+ | b_i => b, | ||
+ | sum_o => sum); | ||
+ | | ||
+ | LEDR <= SW; | ||
+ | |||
+ | end; -- architecture | ||
+ | |||
+ | </code> | ||
+ | |||
+ | <code vhdl top_tb.vhd> | ||
+ | library ieee; | ||
+ | use ieee.std_logic_1164.all; | ||
+ | use ieee.numeric_std.all; | ||
+ | |||
+ | entity top_tb is | ||
+ | end; | ||
+ | |||
+ | architecture beh of top_tb is | ||
+ | |||
+ | component top | ||
+ | port ( | ||
+ | SW: in std_ulogic_vector(9 downto 0); -- Switches | ||
+ | LEDR: out std_ulogic_vector(9 downto 0); -- Red LEDs above switches | ||
+ | HEX0: out std_ulogic_vector(6 downto 0); -- 7 Segment Display | ||
+ | HEX1: out std_ulogic_vector(6 downto 0); -- 7 Segment Display | ||
+ | HEX2: out std_ulogic_vector(6 downto 0) -- 7 Segment Display | ||
+ | ); | ||
+ | end component; | ||
+ | |||
+ | signal number1, number2 : unsigned(4 downto 0); | ||
+ | signal switch : std_ulogic_vector(9 downto 0); | ||
+ | signal hex0, hex1, hex2 : std_ulogic_vector(6 downto 0); | ||
+ | signal ledr : std_ulogic_vector(9 downto 0); | ||
+ | |||
+ | begin | ||
+ | | ||
+ | top_i0 : top | ||
+ | port map ( | ||
+ | SW => switch, | ||
+ | LEDR => ledr, | ||
+ | HEX0 => hex0, | ||
+ | HEX1 => hex1, | ||
+ | HEX2 => hex2); | ||
+ | |||
+ | switch(4 downto 0) <= std_ulogic_vector(number1); | ||
+ | switch(9 downto 5) <= std_ulogic_vector(number2); | ||
+ | | ||
+ | process | ||
+ | begin | ||
+ | number1 <= "00000"; | ||
+ | number2 <= "00000"; | ||
+ | wait for 10 us; | ||
+ | for i in 0 to 31 loop | ||
+ | number1 <= number1 + 1; | ||
+ | for v in 0 to 31 loop | ||
+ | number2 <= number2 + 1; | ||
+ | wait for 10 us; | ||
+ | end loop; | ||
+ | end loop; | ||
+ | end process; | ||
+ | |||
end; -- architecture | end; -- architecture | ||
</code> | </code> |