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dt-code [2024/03/12 00:01] beckmanf add and_gate_arch |
dt-code [2024/03/12 00:19] (current) beckmanf add signal |
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| Listing 2: Structural VHDL code that instantiates and_gate, or_gate and inv_gate | Listing 2: Structural VHDL code that instantiates and_gate, or_gate and inv_gate | ||
| - | Note the signals s1, s2 and s3 which work as internal nets in "mux". The instantiation code introduces the name of the instance. In this example the names of the "and_gate" instances are "and_gate_i0" and "and_gate_i1". The instantiation code instantiates "work.and_gate" which means that there is a component "and_gate" assumed to be in library "work". The "and_gate" component is created in the work library when the corresponding vhdl code that defines the "and_gate" is compiled. | + | The instantiation code introduces the name of the instance. In this example the names of the "and_gate" instances are "and_gate_i0" and "and_gate_i1". The instantiation code instantiates "work.and_gate" which means that there is a component "and_gate" assumed to be in library "work". The "and_gate" component is created in the work library when the corresponding vhdl code that defines the "and_gate" is compiled. |
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| + | ===== Signals ===== | ||
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| + | Note the signals s1, s2 and s3 in listing 2 which work as internal nets in "mux". But it is also possible to assign the value of an input port to a signal. The value of a signal can also be assign to an output port. | ||
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| + | Signals are defined between "architecture" and the following "begin". | ||
| ===== Multiplexer Code - the real thing ===== | ===== Multiplexer Code - the real thing ===== | ||