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dt-code [2011/01/10 12:52] beckmanf Funktionale Beschreibung des Multiplexers eingefügt. |
dt-code [2012/01/11 13:12] beckmanf typos |
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| Line 11: | Line 11: | ||
| a_i : in std_ulogic; | a_i : in std_ulogic; | ||
| b_i : in std_ulogic; | b_i : in std_ulogic; | ||
| - | y_i : out std_ulogic); | + | y_o : out std_ulogic); |
| - | end first; | + | end and_gate; |
| architecture rtl of and_gate is | architecture rtl of and_gate is | ||
| begin | begin | ||
| y_o <= a_i and b_i; | y_o <= a_i and b_i; | ||
| - | end rtl; | + | end architecture rtl; |
| | | ||
| </code> | </code> | ||
| Line 42: | Line 42: | ||
| b_i : in std_ulogic; | b_i : in std_ulogic; | ||
| y_o : out std_ulogic); | y_o : out std_ulogic); | ||
| + | end component; | ||
| | | ||
| component or_gate | component or_gate | ||
| Line 48: | Line 49: | ||
| b_i : in std_ulogic; | b_i : in std_ulogic; | ||
| y_o : out std_ulogic); | y_o : out std_ulogic); | ||
| - | | + | end component; |
| + | | ||
| component inv_gate | component inv_gate | ||
| port( | port( | ||
| a_i : in std_ulogic; | a_i : in std_ulogic; | ||
| y_o : out std_ulogic); | y_o : out std_ulogic); | ||
| - | | + | end component; |
| + | | ||
| signal s1 : std_ulogic; | signal s1 : std_ulogic; | ||
| signal s2 : std_ulogic; | signal s2 : std_ulogic; | ||
| Line 83: | Line 86: | ||
| y_o => y_o); | y_o => y_o); | ||
| - | end mux; | + | end architecture mux; |
| </code> | </code> | ||
| Line 213: | Line 216: | ||
| with s_i select | with s_i select | ||
| y_o <= a_i when '0', | y_o <= a_i when '0', | ||
| - | y_o <= b_i when '1'; | + | b_i when '1'; |
| end rtl-6 | end rtl-6 | ||