library ieee;
use ieee.std_logic_1164.all;
 
entity and_gate is
port(
  a_i : in std_ulogic;
  b_i : in std_ulogic; 
  y_i : out std_ulogic);
end first;
 
architecture rtl of and_gate is
begin
  y_o <= a_i and b_i; 
end rtl; 
 

library ieee;
use ieee.std_logic_1164.all;
 
entity mux is
port (
  a_i : in std_ulogic;
  b_i : in std_ulogic;
  s_i : in std_ulogic;
  y_o : out std_ulogic);
end mux;
 
architecture structure of mux is
 
  component and_gate 
    port(
      a_i : in std_ulogic;
      b_i : in std_ulogic;
      y_o : out std_ulogic);
 
  component or_gate
    port(
      a_i : in std_ulogic;
      b_i : in std_ulogic;
      y_o : out std_ulogic);
 
  component inv_gate
    port(
      a_i : in std_ulogic;
      y_o : out std_ulogic);
 
  signal s1 : std_ulogic;
  signal s2 : std_ulogic;
  signal s3 : std_ulogic;     
 
begin
 
  inv_gate_i0 : inv_gate
  port map(
    a_i => s_i,
    y_o => s1);
 
  and_gate_i0 : and_gate
  port map(
    a_i => s1,
    b_i => a_i,
    y_o => s2);
 
  and_gate_i1 : and_gate
  port map(
    a_i => s_i,
    b_i => b_i,
    y_o => s3);
 
  or_gate_i0 : or_gate
  port map(
    a_i => s2,
    b_i => s3,
    y_o => y_o);
 
end mux;