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dt-code-congen [2011/04/07 12:32] (current)
beckmanf created
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 +====== Konstanten ======
 +
 +Im VHDL Code können Konstanten definiert werden, die zur Synthesezeit bekannt sind. 
 +Mit diesen Konstanten können deshalb Schaltungen parametrisiert werden. ​
 +
 +
 +<code vhdl>
 +
 +architecture struct of top is
 +
 +constant adderinputwidth_c : integer := 8;
 +
 +signal op1, op2, res: unsigned(adderinputwidth_c-1 downto 0);
 +
 +begin
 +
 +res <= op1 + op2; 
 +
 +-- und anderer Code...
 +
 +end architecture; ​
 +
 +
 +</​code>​
 +
 +====== Generics ======
 +
 +Um auch Schaltungsteile parametriesierbar zu halten gibt es "​Generics"​. Im Beispiel unten
 +ist ein Schieberegister,​ dessen Länge via generic "​n"​ einstellbar ist. 
 +
 +<code vhdl>
 +LIBRARY ieee;
 +USE ieee.std_logic_1164.all;​
 +use ieee.numeric_std.all;​
 +
 +entity shiftreg is
 +  generic(
 +    n : integer); ​
 +  port (
 +    clk_i: ​     in std_ulogic;
 +    par_i: ​     in std_ulogic_vector(n-1 downto 0);
 +    par_o: ​     out std_ulogic_vector(n-1 downto 0);
 +    ser_i: ​     in std_ulogic;
 +    ser_o: ​     out std_ulogic;
 +    sh_i:       in std_ulogic
 +  );
 +end; 
 +
 +architecture rtl of shiftreg is
 +  signal sr : std_ulogic_vector(n-1 downto 0);
 +begin
 +
 +sr_p : process(clk_i)
 +begin
 +  if rising_edge(clk_i) then
 +    if (sh_i = '​1'​) then
 +      sr(n-2 downto 0) <= sr(n-1 downto 1);
 +      sr(n-1) <= ser_i;
 +    else
 +      sr <= par_i;
 +    end if;
 +  end if;
 +end process sr_p;
 +
 +par_o <= sr;
 +ser_o <= sr(0);
 +
 +end architecture rtl;
 +</​code>​
 +
 +Bei der Instantiierung wird dann der Genericwert bei der Synthesezeit festgelegt. ​
 +
 +<code vhdl>
 +
 +architecture struct of top is
 +
 +component shiftreg is
 +  generic(
 +    n : integer); ​
 +  port (
 +    clk_i: ​     in std_ulogic;
 +    par_i: ​     in std_ulogic_vector(n-1 downto 0);
 +    par_o: ​     out std_ulogic_vector(n-1 downto 0);
 +    ser_i: ​     in std_ulogic;
 +    ser_o: ​     out std_ulogic;
 +    sh_i:       in std_ulogic
 +  );
 +end component;
 +
 +begin
 +
 +sr_i0 : shiftreg
 +generic map (
 +  n => 10)
 +port map (
 +  clk_i => clk,
 +  par_i => parallel_input,​
 +  par_o => parallel_output,​
 +  ser_i => serial_input,​
 +  ser_o => serial_output,​
 +  sh_i  => shift_control_signal); ​
 +
 +end architecture;​
 + 
 +</​code>​
 +
 +
 +
 +
 +
 +
  
  • dt-code-congen.txt
  • Last modified: 2011/04/07 12:32
  • by beckmanf