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dt-code-sequ [2012/01/18 11:08] beckmanf typos |
dt-code-sequ [2012/06/11 10:35] beckmanf concurrent flipflop |
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in_i : in std_ulogic; | in_i : in std_ulogic; | ||
out_o : out std_ulogic); | out_o : out std_ulogic); | ||
- | end; | + | end entity flipflop; |
architecture rtl of fliplfop is | architecture rtl of fliplfop is | ||
Line 33: | Line 33: | ||
out_o <= q; | out_o <= q; | ||
- | end; | + | end architecture rtl; |
+ | </code> | ||
+ | Ein Flipflop kann alternativ mit einem concurrent statement beschrieben werden. | ||
+ | |||
+ | <code vhdl> | ||
+ | entity flipflop is | ||
+ | port( | ||
+ | clk : in std_ulogic; | ||
+ | reset_n : in std_ulogic; | ||
+ | in_i : in std_ulogic; | ||
+ | out_o : out std_ulogic); | ||
+ | end entity flipflop; | ||
+ | |||
+ | architecture rtl of fliplfop is | ||
+ | signal q : std_ulogic; | ||
+ | begin | ||
+ | |||
+ | q <= '0' when reset_n = '0' else in_i when rising_edge(clk); | ||
+ | |||
+ | out_o <= q; | ||
+ | |||
+ | end architecture rtl; | ||
</code> | </code> | ||
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