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--- dt-code-sequ [2012/01/18 11:08]
beckmanf typos
+++ dt-code-sequ [2014/01/08 10:58]
beckmanf flipflop process -> concurrent
@@ Line 16: / Line 16: @@
   in_i     :        in std_ulogic;
   out_o    :        out std_ulogic);
-end;
+end entity flipflop;
 architecture rtl of fliplfop is
@@ Line 33: / Line 33: @@
 out_o <= q;
-end;
+end architecture rtl;
+</code>
+Ein Flipflop kann alternativ mit einem concurrent statement beschrieben werden.
+<code vhdl>
+entity flipflop is
+  port(
+  clk      :        in std_ulogic;
+  reset_n  :        in std_ulogic;
+  in_i     :        in std_ulogic;
+  out_o    :        out std_ulogic);
+end entity flipflop;
+architecture rtl of fliplfop is
+  signal q : std_ulogic;
+begin
+q <= '0' when reset_n = '0' else in_i when rising_edge(clk);
+out_o <= q;
+end architecture rtl;
 </code>
@@ Line 76: / Line 97: @@
 entity strangecnt is
   port (
-    clk_i                   : in std_ulogic;
+    clk                     : in std_ulogic;
-    reset_ni                : in std_ulogic;
+    rst_n                   : in std_ulogic;
     s_i                     : in std_ulogic;
     cnt0_o                  : out std_ulogic;
@@ Line 88: / Line 109: @@
   signal l : std_ulogic;
 begin
-  seq_p : process(clk_i, reset_ni)
-  begin
+  c0 <= '0' when rst_n = '0' else c0_new when rising_edge(clk);
-    if reset_ni = '0' then
+  c1 <= '0' when rst_n = '0' else c1_new when rising_edge(clk);
-      c0 <= '0';
-      c1 <= '0';
-    elsif rising_edge(clk_i) then
-      c0 <= c0_new;
-      c1 <= c1_new;
-    end if;
-  end process seq_p;
   c0_new <= not c0;