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--- dt-code-statem [2011/01/13 09:17]
beckmanf created
+++ dt-code-statem [2011/05/05 11:42]
beckmanf Testbench eingefügt
@@ Line 19: / Line 19: @@
 end;
-architecture rtl of edge is
+architecture rtl of automat is
   type state_type is (start_s, erste_eins_s, null_in_der_mitte_s, fertig_s);
   signal current_state, next_state : state_type;
@@ Line 68: / Line 68: @@
 end architecture;
 </code>
+Und hier ist eine geeignete Testbench:
+<code vhdl>
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.math_real.all;
+entity automat_tb is
+  port (
+    clk_i:            in std_ulogic;
+    reset_ni:         in std_ulogic;
+    in_i:             in std_ulogic;
+    out_o:            out std_ulogic
+  );
+end;
+architecture beh of automat_tb is
+component automat is
+  port (
+    clk_i:            in std_ulogic;
+    reset_ni:         in std_ulogic;
+    in_i:             in std_ulogic;
+    out_o:            out std_ulogic
+  );
+end component;
+signal clk, reset, stim, output : std_ulogic;
+begin
+-- This process generates the clock
+clk_p : process
+begin
+  clk <= '0';
+  wait for 5 ns;
+  clk <= '1';
+  wait for 5 ns;
+end process;
+-- Here the automat is instantiated as the device under test
+dut: automat
+port map (
+  clk_i           => clk,
+  reset_ni        => reset,
+  in_i            => stim,
+  out_o           => output
+);
+test : process
+begin
+  reset <= '0';
+  -- Wait for some time
+  wait for 100 ns;
+  wait until falling_edge(clk);
+  -- Reset Release
+  reset <= '1';
+  -- Now the positive 101 Sequence
+  stim <= '1';
+  wait until falling_edge(clk);
+  stim <= '0';
+  wait until falling_edge(clk);
+  stim <= '1';
+  wait until falling_edge(clk);
+  stim <= '0';
+  wait until falling_edge(clk);
+  wait until falling_edge(clk);
+  wait;
+end process test;
+end architecture;
+</code>