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dt-code-statem [2011/05/05 11:42]
beckmanf Testbench eingefügt
dt-code-statem [2011/05/10 11:26] (current)
beckmanf added more tests
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 end architecture;​ end architecture;​
 </​code>​ </​code>​
 +
 +The previous testbench only produced a stimuli sequence which results in the output going high. The testbench did not check the output signal however. For checking the output, the assert command is used in VHDL. The following modified testbench checks the output. ​
 +
 +<code vhdl>
 +
 +test : process
 +begin
 +  reset <= '​0';​
 +  -- Wait for some time
 +  wait for 100 ns; 
 +  report "​Checking Reset Value";​
 +  assert output = '​0'​ report "​Resetvalue of output is not o.k." severity error;
 +  wait until falling_edge(clk);​
 +  -- Reset Release
 +  reset <= '​1'; ​
 +  -- Now the positive 101 Sequence
 +  stim <= '​1';​
 +  wait until falling_edge(clk);​
 +  assert output = '​0'​ report "​Output is not zero after first one" severity error;
 +  stim <= '​0';​
 +  wait until falling_edge(clk);​
 +  assert output = '​0'​ report "​Output is not zero after zero in the middle"​ severity error;
 +  stim <= '​1';​
 +  wait until falling_edge(clk);​
 +  assert output = '​1'​ report "​Output is not O.K." severity error;
 +  stim <= '​0';​
 +  wait until falling_edge(clk);​
 +  wait until falling_edge(clk);​
 +
 +  assert false report "End of Simulation"​ severity failure;
 +end process test; 
 +</​code>​
 +
 +In addition the simulation is stopped with the final assert false statement. The previous stimuli sequence only shows one positive example for the good case. It is not tested that other sequences may also trigger the output going high. 
 +
 +The following code test process produces a random sequence for the input pattern. It is checked if the "​101"​ sequence is in the random pattern. With "​101"​ the output is checked for "​1",​ otherwise the output has to be "​0"​. ​
 +
 +<code vhdl>
 +use ieee.math_real.all;​
 +
 +--- architecture and begin follows
 +
 +test2_p : process ​
 +  variable zufall : real;
 +  variable seed1 : integer := 5;
 +  variable seed2 : integer := 17; 
 +  variable inp_letzter,​ inp_vorletzter : std_ulogic; ​
 +begin
 +  reset <= '​0';​
 +  wait for 10 ns; 
 +  reset <= '​1'; ​
 +  for count in  0 to 1500 loop
 +    wait until falling_edge(clk);​
 +    if (inp_vorletzter = '​1'​ and inp_letzter = '​0'​ and stim = '​1'​) then
 +      assert output = '​1'​ report "​Fehler:​ Habe eine Eins erwartet"​ severity error;
 +    else
 +      assert output = '​0'​ report "​Fehler am Ausgang - Null erwartet"​ severity error; ​
 +    end if; 
 +    inp_vorletzter := inp_letzter;​
 +    inp_letzter := stim; 
 +    uniform(seed1,​ seed2, zufall); ​   ​
 +    if (zufall <= 0.5) then 
 +      stim <= '​0';​
 +    else
 +      stim <= '​1';​
 +    end if;
 +  end loop;  ​
 +  assert false report "End of Simulation"​ severity failure; ​
 +end process test2_p; ​
 +</​code> ​
 +
 +This code simulates 1500 cycles. Also this code does not test all possible input sequences - which is not possible anyway. Without knowledge about the internal state it is not possible to do a 100% verification of the statemachine implementation. ​
  
  • dt-code-statem.txt
  • Last modified: 2011/05/10 11:26
  • by beckmanf