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+=== Code für Vorwärts-/Rückwärtszähler ===
+<code vhdl top.vhd>
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity top is
+  port (
+    CLOCK_50:   in  std_ulogic;                    -- 50 MHz Clock input
+    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
+    KEY:        in  std_ulogic_vector(3 downto 0); -- Keys
+    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
+    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
+    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
+    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
+  );
+end;
+architecture struct of top is
+  component bin2seg is
+    port (
+      number_i:       in  unsigned(3 downto 0);
+      seg_o:          out std_ulogic_vector(6 downto 0)
+    );
+  end component;
+  component counter is
+    port (
+      clk_i:          in  std_ulogic;
+      reset_ni:       in  std_ulogic;
+      enable_i:       in  std_ulogic;
+      up_i:           in  std_ulogic;
+      count_o:        out unsigned(7 downto 0)
+    );
+  end component;
+  component edge is
+    port (
+      clk_i:          in  std_ulogic;
+      reset_ni:       in  std_ulogic;
+      key_i:          in  std_ulogic;
+      edge_o:         out std_ulogic
+    );
+  end component;
+  signal count : unsigned(7 downto 0);
+  signal enable : std_ulogic;
+begin
+  bin2seg_i0 : bin2seg
+    port map (
+      number_i => count(3 downto 0),
+      seg_o    => HEX0);
+  bin2seg_i1 : bin2seg
+    port map (
+      number_i => count(7 downto 4),
+      seg_o    => HEX1);
+  counter_i0 : counter
+    port map (
+      clk_i    => CLOCK_50,
+      reset_ni => KEY(1),
+      enable_i => enable,
+      up_i     => KEY(2),
+      count_o  => count);
+  edge_i0 : edge
+    port map (
+      clk_i         => CLOCK_50,
+      reset_ni      => KEY(1),
+      key_i         => KEY(0),
+      edge_o        => enable);
+  LEDR(7 downto 0) <= std_ulogic_vector(count);
+  LEDR(9 downto 8) <= "00";
+  HEX2 <= "1111111";
+end; -- architecture
+</code>
+<code vhdl top_tb.vhd>
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity top_tb is
+end;
+architecture beh of top_tb is
+  component top
+  port (
+    CLOCK_50:   in  std_ulogic;
+    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
+    KEY:        in  std_ulogic_vector(3 downto 0);
+    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
+    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
+    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
+    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
+    );
+  end component;
+  signal clk, reset_n : std_ulogic;
+  signal inc, dir       : std_ulogic;
+  signal switch : std_ulogic_vector(9 downto 0);
+  signal key    : std_ulogic_vector(3 downto 0);
+  signal ledr   : std_ulogic_vector(9 downto 0);
+  signal hex0, hex1, hex2 : std_ulogic_vector(6 downto 0);
+begin
+  top_i0 : top
+    port map (
+      CLOCK_50            => clk,
+      SW                  => switch,
+      KEY                 => key,
+      LEDR                => ledr,
+      HEX0                => hex0,
+      HEX1                => hex1,
+      HEX2                => hex2);
+  key(0) <= inc;
+  key(1) <= reset_n;
+  key(2) <= dir;
+  key(3) <= '0';
+  clk_p : process
+  begin
+    clk <= '0';
+    wait for 1 us;
+    clk <= '1';
+    wait for 1 us;
+  end process clk_p;
+  reset_p : process
+  begin
+    reset_n <= '0';
+    wait for 15500 ns;
+    reset_n <= '1';
+    wait;
+  end process reset_p;
+  incr_p : process
+  begin
+    inc <= '1';
+    dir <= '1';
+    wait for 25100 ns;
+    for v in 0 to 1 loop
+    for i in 0 to 3 loop
+      inc <= '0';
+      wait for 20 us;
+      inc <= '1';
+      wait for 20 us;
+    end loop;
+    dir <= not dir;
+    end loop;
+  end process incr_p;
+  switch <= "0000000000";
+end; -- architecture
+</code>