Code für qdec

qdec.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
-- Finite State Machine (FSM) for rising edge detection
-- The edge_o signal will go to "1", when there is a 01 sequence
-- at the key_i input. 
 
entity qdec is 
  port (
    clk_i:                in std_ulogic;
    reset_ni:             in std_ulogic;
    s1_i:                 in std_ulogic;
    s2_i:                 in std_ulogic;  
    rising_edge_s1_i:     in std_ulogic; 
    falling_edge_s1_i:    in std_ulogic;
    rising_edge_s2_i:     in std_ulogic; 
    falling_edge_s2_i:    in std_ulogic;
    up_o:                 out std_ulogic;
    enable_o:             out std_ulogic  
  );
end; 
 
architecture rtl of qdec is  
  type state_type is (XXXX_s);
  signal current_state, next_state : state_type;
begin
 
  next_state_and_output_p : process(current_state, s1_i, s2_i, rising_edge_s1_i, 
                                    falling_edge_s1_i, rising_edge_s2_i, falling_edge_s2_i)
  begin
    up_o <= '0';
    enable_o <= '0';
    next_state <= current_state; 
    case current_state is
      when XXXX_s =>      
      -- Your code goes here...  
 
      when others => 
        next_state <= current_state; 
    end case; 
  end process next_state_and_output_p;  
 
  -- The sequential process for flipflop instantiation
  -- All signal assignments in this process will result in flipflops.
  state_reg_p : process (clk_i, reset_ni)
  begin
    if reset_ni = '0' then
      current_state <= waiting_s;
    elsif rising_edge(clk_i) then
      current_state <= next_state; 
    end if; 
  end process state_reg_p;      
 
end; -- architecture
top.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity top is 
  port (
    CLOCK_50:   in  std_ulogic;                    -- 50 MHz Clock input
    GPIO_1:     in  std_ulogic_vector(35 downto 0);-- GPIO poins 
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches
    KEY:        in  std_ulogic_vector(3 downto 0); -- Keys
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
  );
end; 
 
architecture struct of top is
 
  component bin2seg is 
    port (
      number_i:       in  unsigned(3 downto 0);
      seg_o:          out std_ulogic_vector(6 downto 0)
    );
  end component;
 
  component counter is 
    port (
      clk_i:          in  std_ulogic;
      reset_ni:       in  std_ulogic;
      enable_i:       in  std_ulogic; 
      up_i:           in  std_ulogic; 
      count_o:        out unsigned(7 downto 0)
    );
  end component;
 
  component qdec is
    port (
      clk_i:             in std_ulogic;
      reset_ni:          in std_ulogic;
      s1_i:              in std_ulogic;
      s2_i:              in std_ulogic; 
      rising_edge_s1_i:  in std_ulogic;
      rising_edge_s2_i:  in std_ulogic;
      falling_edge_s1_i: in std_ulogic;
      falling_edge_s2_i: in std_ulogic; 
      up_o:              out std_ulogic;
      enable_o:          out std_ulogic);
  end component; 
 
  component edge is 
    port (
      clk_i:          in  std_ulogic;
      reset_ni:       in  std_ulogic;
      key_i:          in  std_ulogic;
      falling_edge_o: out std_ulogic; 
      rising_edge_o:  out std_ulogic 
    );
  end component;
 
  signal count : unsigned(7 downto 0);
  signal enable, up : std_ulogic; 
  signal reset_n : std_ulogic;
  signal s1, s2 : std_ulogic;
  signal rising_edge_s1, falling_edge_s1 : std_ulogic;
  signal rising_edge_s2, falling_edge_s2 : std_ulogic; 
 
begin
 
  bin2seg_i0 : bin2seg
    port map (
      number_i => count(3 downto 0),
      seg_o    => HEX0);
 
  bin2seg_i1 : bin2seg
    port map (
      number_i => count(7 downto 4),
      seg_o    => HEX1);
 
  counter_i0 : counter
    port map (
      clk_i    => CLOCK_50,
      reset_ni => reset_n,
      enable_i => enable,
      up_i     => up,
      count_o  => count);
 
  edge_i0 : edge
    port map (
      clk_i         => CLOCK_50,
      reset_ni      => reset_n,
      key_i         => s1,
      rising_edge_o => rising_edge_s1,
      falling_edge_o => falling_edge_s1);
 
  edge_i1 : edge
    port map (
      clk_i         => CLOCK_50,
      reset_ni      => reset_n,
      key_i         => s2,
      rising_edge_o => rising_edge_s2,
      falling_edge_o => falling_edge_s2);
 
  qdec_i0 : qdec
    port map (
      clk_i             => CLOCK_50,
      reset_ni          => reset_n,
      s1_i              => s1,
      s2_i              => s2,
      rising_edge_s1_i  => rising_edge_s1,
      falling_edge_s1_i => falling_edge_s1,
      rising_edge_s2_i  => rising_edge_s2,
      falling_edge_s2_i => falling_edge_s2,
      up_o              => up,
      enable_o          => enable); 
 
  s1 <= GPIO_1(0);
  s2 <= GPIO_1(1); 
  reset_n <= KEY(0);
 
  LEDR(7 downto 0) <= std_ulogic_vector(count);
  LEDR(9 downto 8) <= GPIO_1(1 downto 0); 
  HEX2 <= "1111111";
 
end; -- architecture
top_tb.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity top_tb is
end; 
 
architecture beh of top_tb is
 
  component top 
  port (
    CLOCK_50:   in  std_ulogic;
    GPIO_1:     in  std_ulogic_vector(35 downto 0); 
    SW:         in  std_ulogic_vector(9 downto 0); -- Switches  
    KEY:        in  std_ulogic_vector(3 downto 0);
    LEDR:       out std_ulogic_vector(9 downto 0); -- Red LEDs above switches
    HEX0:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX1:       out std_ulogic_vector(6 downto 0); -- 7 Segment Display
    HEX2:       out std_ulogic_vector(6 downto 0)  -- 7 Segment Display
    );
  end component;
 
  signal clk, reset_n : std_ulogic;
 
  signal switch : std_ulogic_vector(9 downto 0);
  signal key    : std_ulogic_vector(3 downto 0);
  signal ledr   : std_ulogic_vector(9 downto 0);
  signal hex0, hex1, hex2 : std_ulogic_vector(6 downto 0); 
  signal gpio_1 : std_ulogic_vector(35 downto 0);
  signal s1, s2 : std_ulogic; 
 
begin
 
  top_i0 : top
    port map (
      CLOCK_50            => clk,
      GPIO_1              => gpio_1,
      SW                  => switch,
      KEY                 => key,
      LEDR                => ledr,
      HEX0                => hex0,
      HEX1                => hex1,
      HEX2                => hex2);
 
  clk_p : process
  begin
    clk <= '0';
    wait for 1 us;
    clk <= '1';
    wait for 1 us; 
  end process clk_p;
 
  reset_p : process
  begin
    reset_n <= '0';
    wait for 15500 ns; 
    reset_n <= '1';  
    wait; 
  end process reset_p;
 
  s1_p : process
  begin
    for i in 0 to 3 loop
      s1 <= '0';
      wait for 50 us;
      s1 <= '1';
      wait for 50 us;
    end loop; 
    wait for 50 us; 
  end process s1_p;
 
  s2_p : process
  begin
    s2 <= '0';  
    wait for 25 us;
    for i in 0 to 1000 loop
      s2 <= '0';
      wait for 50 us;
      s2 <= '1';
      wait for 50 us;
    end loop; 
    wait; 
  end process s2_p;
 
  GPIO_1(0) <= s1;
  GPIO_1(1) <= s2; 
  GPIO_1(35 downto 2) <= (others => '0'); 
 
  switch <= "0000000000";  
  key(3 downto 1) <= "000"; 
  key(0) <= reset_n;  
 
end; -- architecture
  • dtpr_v4_qdec.txt
  • Last modified: 2010/12/06 17:49
  • by beckmanf